HDL Works is a supplier of front-end VHDL / Verilog design tools,
translators and an FPGA / PCB pin assignment verification tool.
HDL Works has over 15 years experience developing HDL tools.
All tools are available on Windows and Linux operating systems.
ConnTrace is used to view connections between components (including FPGAs) on one or more PCBs and to verify the connections between various PCB's, Independent on how your PCBs are connected (backplanes, connectors and/or rear panels). ConnTrace will present a view of the connections in seconds.
Graphical HDL Design tool for VHDL and (System)Verilog.
Combines block diagrams, state diagrams, truth tables and HDL code.
Supports user defined types in packages, generate statements
The SWISS Army knife for every HDL Design Engineer
It will give you a complete overview of any VHDL or Verilog design in seconds.
Features include verification, linting and HTML generation.
When using large FPGA's on a PCB making sure that the FPGA pins are connected to the right
signals is a cumbersome task.
IO Checker uses rules (based on regular expressions) to match the signal names in both the FPGA and PCB design environment.
A text editor focused at VHDL and Verilog, using a Multiple Document Interface. (Free of charge)
Fujitsu FLDL netlist and FTDL test format translated into a VHDL or Verilog netlist.
Including specific Fujitsu cell libraries like CG31 and CG51.
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