Primitive instances |
LRM §7. |
Verilog has a number of built-in primitives that model gates and switches.
gate_type [ ( strength ) ] [ #( delay ) ] [ instance_name ] [ instance_range ] ( terminal, terminal, ... ); switch_type [ #( delay ) ] [ instance_name ] [ instance_range ] ( terminal, terminal, ... );
The built-in primitives can be instanced in modules to create a structural description of the behaviour of the module. Verilog has the following built-in primitives:
| Name |
Gate Type |
Terminals |
| Logic |
and, nand, or, nor, xor, xnor |
Output, Input(s) |
| Buffer and inverter |
buf, not |
Output(s), Input |
| Tristate logic |
bufif0, bufif1, notif0, notif1 |
Output, Input, Enable |
| Pullup and pulldown |
pullup, pulldown |
Output |
| Name |
Switch Type |
Terminals |
| MOS |
nmos, pmos, rnmos, rpmos |
Output, Input, Enable |
| CMOS |
cmos, rcmos |
Output, Input, N-Enable, P-Enable |
| Bidirectional pass |
tran, rtran |
Inout1, Inout2 |
| Bidirectional pass with control |
tranif0, tranif1, rtranif0, rtranif1 |
Inout1, Inout2, Control |
Only gate primitives may have drive strength. Switch primitives pass the input strength to the output. Resistive switches reduce the strength as it passes through.
The delay represents the propagation delay through a primitive. The default delay is zero.
and u1 (Q, A, B); and #(2.1, 2.8) u2 (Q, A, B); and (pull0, strong1) (Q, A, B);