Operators perform an operation on one or two operands.

Syntax:

// operator operand
+   -                           // sign
!                               // logical negation
~                               // bitwise negation
&   ~&   |   ~|   ^   ~^   ^~   // reduction (~^ and ^~ are equivalent)

// operand operator operand
+   -   *   /   **              // arithmetic
%                               // modulus
>   >=   <   <=                 // comparison
&&   ||                         // logical
==   !=                         // logical equality
===   !===                      // case equality
&   |   ^   ^~   ~^             // bitwise (^~ and ~^ are equivalent)
<<   >>   <<<   >>>             // shift

// miscellaneous operators
?   :                           // Sel ? M : N;  if Sel is true, M: else N
{}                              // {M, N};  concatenate M to N
{{}}                            // {N{M}};  replicate M N-times
->                              // ->M;  trigger an event on an event data type

Description:

Operators are used in expressions to produce values from operands. The operators in Verilog are similar to those in the C programming language.

The operands may be either net or register data types. They may be scalar, vector, or bit selects of a vector.

Operators which return a True/False result will return a 1-bit value where 1 is True, 0 is False, and X is indeterminate.

The operator precedence is:

+  -  !  ~ (unary)     // highest precedence
*  /  %  **
+  -  (binary)
<<  >>  <<<  >>>
<  <=  >  >=
==  !=  ===  !==
&  ~&
^  ~^
|  ~|
&&
||
?:                     // lowest precedence

Example:

A + B
A && B || C && D   // same as (A && B) || (C && D)
~4'b1001           // Gives 4'b0110
&4'hF              // Gives 1'b1 as all bits are 1

Notes:

• Use brackets rather than operator precedence to form expressions.

See also:

Number