Specify defines a delay across a module.

Syntax:

specify
  [ specparam_declaration; ]
  [ path_declaration; ]
  [ system_timing_check; ]
endspecify

Description:

The specify block describes paths across the module and assigns delays to those paths. It performs also timing checks like setup and hold times. The specify block is declared inside the module declaration.

The path declaration describes the path between the source and destination signal inside the module and assigns the delays to this path. The path can be a simple path, edge sensitive path or state-dependent path. The path is on the left-hand side of the statement and the delays are on the right-hand side. The delay values must be constant expressions or specparams, and may be of the form min:typ:max.

A simple path describes a path between an input and output port. An edge sensitive path models the delay timing only when a specified edge occurs at the source signal. A state-dependent path assigns the delay only when a specified codition is True. In this condition the keyword ifnone is used to specify a default delay for when all conditions for the path are False.

Verilog-2001 adds two keywords, pulsestyle_onevent and pulsestyle_ondetect for pulse error propagation for pin-to-pin path delays. A pulse is a glitch on the inputs of a model path that is less than the delay of the path. With on-event the leading and trailing edge of an input pulse propagate as a logic X to the path outputs. The timing of this X is the same as if the input changes had propagated to the output. On-detect is more pessimistic. As with on-event, on-detect changes the leading and trailing edge into a logic X to the path outputs, but the time of the leading edge is changed to occur immediately upon detection of the pulse.

Verilog-2001 provides a mechanism to have a logic X pulse propagate to the output to indicate that a negative pulse had occured. A negative pulse is where the trailing edge of the pulse would occur prior to the leading edge. In Verilog-1995 negative pulses were cancelled. Two keywords are used to explicitly enable or disable negative pulse propagation: showcancelled and noshowcancelled.

System timing checks may be used only in specify blocks. For an overview of the possible timing checks see System Timing Checks.

Example:

specify 
  specparam T1 = 3:4:5,
            T2 = 2:3:4;
  (A => Y) = (T1, T2);                 // Simple path
  (posedge Clk *> Q +: D) = (3, 5);    // Edge sensitive path
  if (Exp = 2'b00) (X *> Z) = 4;
  if (Exp = 2'b01) (X *> Z) = 3.5;
  ifnone (X *> Z) = 3;                 // State-dependent path
  pulsestyle_ondetect Q;               // Verilog-2001
  (D => Q) = (4, 6);
  showcancelled S;                     // Verilog-2001
  (R => S) = (2, 3)
  $setup(D, posedge Clk, 2.8);         // System timing check
endspecify 

See also:

Specparam, Timing checks