A task groups statements together.

Syntax:

task [ automatic ] task_name;
  port_declaration
  [ local_declaration ] 
  statement
endtask 

Description:

A task groups statements together to partition large blocks of statements, or to execute a common sequence of statements from several places. Declarations within a task are statically allocated, and are shared by all task calls.

A task may have any number (including none) of input, output, and inout port declarations.

The port declarations (including inputs and inouts) may be declared as registers. If it is not declared explicity, the port is declared implicity as a reg with the same size as the corresponding port.

The statements must be enclosed in a begin-end or fork-join block if the task contains more than one statement.

A task can be declared as automatic (Verilog-2001), which allows the task to be called recursively. Declarations within the task will be allocated dynamically for each concurrent task call. Declarations within an automatic task cannot be accessed by hierarchical references.

Example:

task ReadRam;
  input [AddrWidth-1:0] Address;
  output [DataWidth-1:0] Data;
  begin
    RamAddress = Address;
    Read = 1;
    #20 Data = RamData;
    Read = 0;
  end
endtask 

Notes:

• Tasks can contain timing controls.
• Tasks may be disabled.
• The ports of a task are not defined in brackets after the word task as in a module declaration.

See also:

Function, Task enable