HDL WORKS PRESENTS EASE 9.0
February 2018, HDL Works announces the release and immediate availability of
EASE 9.0, the Graphical HDL Design tool.
EASE is the most intuitive Graphical HDL Design Entry tool in the industry. Providing the user with a better means of communication, documentation, design entry and modification for any HDL design targeted for FPGA or ASIC. With its four integrated editors (block diagram, state diagram, truth table and text editors) EASE offers a suitable design entry for every HDL requirement. It includes integration with the industry standard revision control system Subversion for real multi-user support.
What's new in EASE 9.0
Multiple diagrams editors open at the same time
In Ease 9.0 it is possible to have multiple editor windows (and of different types) open at the same time. By default they will be shown as tab pages in the editor, but it is possible to undock the tab pages so you can place them in any way you like (e.g. side by side or on different monitors). When you open a diagram from the browser, and this diagram is not yet open in an existing editor, a new editor window will be opened. When you navigate to another diagram inside an existing editor window, you will remain within this editor. It is possible to have the same diagram open in multiple windows.
When an editor window is detached from the main window it will show its own search, lint and verify tabs.
Improved VCM revision log
It is now possible to select the begin and end date (or first and last revision) to be shown in the log window. The log entries are now shown in table view with 3 columns: user who performed the commit, commit date and the message (abbreviated to single line). The full message and the objects to which this message refer are at the bottom on the log.
Improved VCM performance
When performing VCM actions on multiple objects in the same library the actions will be bundled to reduce the number of client/server actions. After some of the VCM actions (like commit for a library units inside one library) we now perform an incremental (partial) reload instead of a full project reload.
Generate statements can use attributes of signals to define the for-loop range. When using VHDL direct instantiations the architecture to use can be specified for each component. VHDL import now supports package declarations/bodies inside an entity declaration. Added an option to the entity properties dialog to not generate VHDL USE clauses for instantiations of the entity. Sometimes needed when using precompiled libraries (e.g. provided by Xilinx).
Availability and Pricing
EASE 9.0 is available now. Prices begin at € 4800 for a perpetual license. EASE can be downloaded and evaluated freely from the HDL Works website.
About HDL Works
HDL Works develops and markets high-performance, intuitive tools for complex HDL design across a wide spectrum of applications. Its software products are available for Linux and Windows platforms. HDL Works currently holds ConnTrace, EASE, HDL Companion, IO Checker and Scriptum in its product portfolio. Headquartered in Ede, The Netherlands, HDL Works is privately held.HDL Works BV
6716 BX Ede
ConnTrace, EASE, HDL Companion, IO Checker and Scriptum are trademarks of HDL Works.