Problems fixed in EASE 9.0 Revision 6

2008 EASE will crash when doing an unselect in the FSM labels dialog 9.0.6 An unselect of unnamed label of an action in the FSM Labels dialog followed by an OK will cause EASE to crash.
2007 No library and use clause generated for instantiation inside generate statement 9.0.6 As title
2003 Ease crashes when deleting a linked library 9.0.5 Ease crashes when deleting a linked library which was restored with an undo/redo
2000 Ease crashes when undo/redo action is initiated during wiring 9.0.5 As title
1994 Connection label not updated after change to port/net name 9.0.5 When a net connection refers to the the net name (%n) and the name of the net (or its driving port if it is a virtual net) changes the connection label is not updated and still contains the name of the old net (or driving port).
1991 Crash after moving objects 9.0.5 Moving a component and some wires simultaneously can cause EASE to crash crash in specific situations
1983 Incorrect Verilog 95 parameter list generated for instance when actual value specified 9.0.5 Verilog 95 uses a positional list for parameter actual values in instantiations. This means we cannot skip parameters that do not have an actual value if later in the parameter list one of the parameters does have an actual value. This defect was introduced when fixing defect 1926. In some cases defect 1926 will appear again.
1971 Installer that supports silent install (MSI /q and /qn options) 9.0.4 Trying to perform a silent install results in an error.
1970 VHDL parser crash after syntax error (generic type) 9.0.4 When a generic type is used the actual type will refer to the first instantiation. If the architecture containing the instantiation contains syntax errors the actual type will be deleted, but the instantiated entity will still refer to the deleted type information causing a crash.
1969 Incorrect VHDL CP7 lint message 9.0.4 When a user has used ieee.numeric_std_unsigned, the comparison operator for std_logic_vector is overloaded to allow numeric matches, even when the vector lengths do not match. In this case no CP7 lint message should be issued.
1968 VHDL linter CP7 false positive 9.0.4 Multi dimensional types were not handled correctly.
1964 Update generated HDL should update after VCM (uncheckout) action 9.0.4 HDL Generation time stamps should be cleared after a VCM action.
1951 Lint from the top level marker ignores HDL Text files 9.0.4 As title
1962 Import subtree should have option to disable package import 9.0.3 It should be possible to disable import of packages when importing a subtree from another project. In some cases you want to import a subtree from an older project and you don't want the enhancements/fixes in the packages to be lost.
1958 Incorrect VHDL generated for a multi dimensional array 9.0.3 Extra parenthesis are generated when using a type defined are an array of std_logic_vector.
1957 Crash in VHDL linter when declaration refers to itself 9.0.3 Defining an signal range using an attribute referring to the signal itself would cause a crash.
1955 Missing semicolon at end of use clause causes fuzzy parser to fail 9.0.3 If a use clause is not ended with a semicolon the fuzzy parser will miss the next object.
1953 Incorrect VHDL-1724 parser error 9.0.3 Target of simple force assignment cannot be a member of a resolved composite signal
1954 When creating a new instance changes to the instance generic are lost 9.0.2 Changes were not saved for the new instance.
1952 Text file content lost during VCM actions 9.0.2 The status of text files added to a library is not correct (modified status). This will cause loss of data when performing a check-in operation.
1946 Scriptum window not raised when opening HDL file architecture 9.0.2 The Scriptum window is not raised when you open an HDL file architecture by double clicking on a component in the block diagram editor.
1939 Hot error navigation to HDL declaration in large tables 9.0.1 Hot error navigation to HDL declaration should highlight the appropriate HDL declaration
1938 Port mode not inverted 9.0.1 When copying a port from one component to another using drag & drop while both SHIFT and CTRL are pressed the port is not rotated.
1937 Port added to instance with custom layout will move to other position 9.0.1 When adding a port to an instance with custom layout the port will be moved to the default position on the entity instead of staying in the place where it was added.
1936 VHDL Context reference incorrectly generated 9.0.1 Code of the context reference appears in use clauses
1935 Package declarations inside other units (packages, entities, architectures) are not supported 9.0.1 In VHDL 2008 package declarations (and package instantiations) are allowed inside other units.
1934 Verification false positive: net needs a resolution function 9.0.1 An incorrect message is issued when multiple components have a generate statement.
1932 Allow hierarchical tracing of component port that is not connected to a net 9.0.1 If a component port is not connected to a net (constant value tag, open tag, or not connected at all) it is not possible to perform hierarchical highlighting.
1931 Port connection label not updated when net name changes 9.0.1 When a port has a net connection property, the net name will be part of the net connection label. However, this label is not (immediately) updated when the net name is changed.
1930 External entity contains link to deleted external HDL file 9.0.1 Added option to entity property dialog (General page) to allow the user to delete the link. This option will only show if a link to a deleted external HDL file is present.
1926 Verilog parameters using the default value 9.0.1 When instantiating Verilog module the default values for parameters should not be added to the instantiation statement
1922 More flexible range support for for-generate statement 9.0.1 Currently it is not possible to specify a range like:
This should also be supported.
1921 VHDL parser crash on syntax error 9.0.1 Parse could crash on an incomplete range definition.
1918 Zoom settings not restored correctly after opening a diagram 9.0.1 Seems to work correctly if no other diagrams are open.
1917 VHDL import incorrectly imports constructs that should not be imported 9.0.1 When a formal is used more than once in a port map only one of the connections is actually connected and the others are silently ignored.
1916 Add shortcut to toggle process port sensitivity 9.0.1 Added shortcut using key sequence T, S
This only works for VHDL as Verilog is not a simple on/off switch (posedge/negedge).
1915 Relative paths to external HDL files and external documents incorrect after save as 9.0.1 For external HDL files and external documents we will now set an extra property containing the canonical path of the external file. If the file cannot be found using the regular path (either relative path or path containing environment variables), we will try to show the correct path based on the information in the canonical path environment variable when the user opens the dialog.
1906 Autoconnect ports creates net with CBN tags while wire option is selected 9.0.1 When trying to connect ports using the settings
- All (matching)
- Wire
inside a diagram that contains other nets connected using CBN tags the new net will also be created using CBN tags instead of using wires as selected.
1901 Option to remove unmodified temporary HDL files when closing a projec 9.0.1 Added user option (Misc page).
If files are delete a message indicating the number of removed files will be printed in the console window.
1895 CBN tag dialog shows duplicate entries when virtual nets are involved 9.0.1 There can be several (virtual) Ease nets that have the same name (e.g. when a bus contains rippers and the destination nets are virtual). When editing the properties of a CBN tag the values in the drop down box are shown by name so there are multiple entries with the same name.
1894 Nets properties dialog does not deal very well with virtual nets 9.0.1 When editing multiple nets using the "Nets properties" dialog (right click in sheet and select "Nets properties...") you run into problems when the diagram contains virtual nets (e.g. when using bus rippers).
1881 Highlight open or constant value tag port 9.0.1 When highlighting a net through the hierarchy the highlighting stops at a port that is not connected to a net. Highlighting this port (can be open or have a constant value tag) would be useful.
1875 Support for backup/restore 9.0.1 Implemented simple backup/restore mechanism. We cannot deal with versioned projects/libraries, so everything will be 'flat' (linked and managed libraries will be resolved).
1871 Option to keep use clause when deleting a library 9.0.1 When deleting a library all use clauses that refer to packages from this library will also removed from a project when they are not read-only. When these use clauses are read-only they get an error status, or be automatically remapped to another version of the deleted library (if present). When you delete a library with entities, the components referring to those entities are not deleted (but mention ). But use clauses are deleted.
1870 It should not be possible to use the same version of 2 managed libraries in a project 9.0.1 When you have a managed library in a project you cannot add the library again (same branch or tag). However when there are different versions present you can select an already used tag or branch in the project. Which is not useful and they will point to the same user files directory.
1868 Improve option field in the project properties for an HDL header 9.0.1 The default is to use the built-in headers by setting no file. If you want no headers at all you need to pass empty files. Perhaps a radio group with 'None', 'Built-in' and 'File' would be more obvious.
1867 3 empty lines before each generated entity 9.0.1 The code generate is inconsistent for the number of empty lines generated. When there are pragmas used at that point there are no extra lines added.
1860 Add option to entity to use component declaration 9.0.1 In a project which is using direct instantiations it would be useful to still use a component decl. for a specific entity, without have to set this for the whole library.
1856 HDL Signal declaration dialog name checking to strict. 9.0.1 Checking should only be done in the current architecture and its entity
1849 Add more info to 'Help about' dialog 9.0.1 From the 'Help about' dialog it should be possible to check if new versions/revisions are available. Also it should be possible to open a browser on a page showing the changes made in these new versions/revisions.
1842 When creating a new Subversion tag please show the most recent tag in the "Existing tags" field 9.0.1 The tag numbers are ordered alphabetically. Please select the most recent one (highest version number) when the dialog opens.
1840 When creating a new Subversion tag please show the most recent tag in the "Existing tags" field 9.0.1 In dialogs showing a tree list (like packages uses and Import subtree) it would be nice to have shortcuts for the search (find, next, prev) functions.
1836 Allow a dummy entity + architectures 9.0.1 Allow a dummy entity for which no HDL is generated en which is never verified. So it can be used as a placeholder for other components.
1829 Show information for all objects in VCM status log 9.0.1 There should be an option in the VCM status log to show information for all objects (also those that are not modified or do not need update). Extra information (like version number and tag number(s) would also be useful).
1828 Improved VCM status log (in table format) 9.0.1 Status log ontains a lot of unnecessary lines. It would be easier (also for export to a spreadsheet) if the information was formatted in table form.
1822 Objects in the database brower cannot be found when parent is not expanded 9.0.1 Entity objects are not created for collapsed database library objects. So they cannot be found by the widget find function.
1821 Virtual record port copy improvement 9.0.1 Whey copying port with virtual record type using drag + SHIFT key, direction of virtual record elements should change
1813 Handle multiple objects in a single VCM transaction 9.0.1 Please commit the changes of objects in the same library in a single transaction.
1807 Wire constraint incorrectly translated on a ripper 9.0.1 VHDL code for multi dimensional arrays incorrectly imported to a ripper.
1796 When moving a port with a single wire the wire is reduced to a short stub 9.0.1 Why not leave the wire length as it is.
1786 Allow constant value tag on a bus ripper 9.0.1 Some times it is necessary to assign a constant value to a part of an array.
1745 A simple way to add 0, '0' or (OTHERS => '0') to a constant value tag. 9.0.1 Helps to assign bit, vector and integer signals in one action.
1691 Improve SVN log to be more like Turtoise log 9.0.1 The turtoise log uses a number of columns which make it easier to grasp than the current text log we use.
1687 Incremental reload after VCM check-in 9.0.1 It should be sufficient to only reload the changed library units, when only they have changed
1378 Add more shortcuts (keyboard accelerators) 9.0.1 Deprecated key 'U' as shortcut to add an Open tag in the block diagram editor. Use key sequence 'A', 'U' to add an Open tag. Key 'U' is now used as first character in key sequences used for Update actions ('U', 'M' => Update from marker).
1377 Placement of selected terminal ports 9.0.1 By default terminal ports are placed at the left hand or right hand side of the sheet. In some cases an instance port (for an instance somewhere in the middle of the diagram) is connected directly to a terminal ports (and no other ports connected to the same net). In this case it would be nice if the terminal port would be placed immediately beside the instance port (to prevent a lot of wires).
615 Manual reroute of a net 9.0.1 Added 'Disconnect' entry to port context menu. The 'Disconnect' entry will only be enabled when the port has no tag and is connected to a net but not placed (so it has an 'unconnected' wire attached to it).
564 Multiple diagrams open in the editor 9.0.1 Allow multiple diagrams to be open in different editors at the same time.
396 Graphical indication for process ports on sensititvity list 9.0.1 It would be nice to have a graphical indication of which ports in a process are in the sensitivity list.
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