Problems fixed in EASE 9.1 Rev 8

Fixed potential crash when trying to delete a package 9.1.8 A crash could appear when deleting a package when there are still package uses for this package at architecture level.
2094 Bindings for nested VHDL configurations are lost during load 9.1.8 When inside a VHDL configuration an instantiation is bound to another configuration the data is saved correctly but after loading the project again the bindings for the nested configuration are no longer correct.
2077 VHDL type name reference should keep original case instead of using case of definition 9.1.7 VHDL-2008 package std_logic_1164 contains:
     subtype STD_LOGIC is resolved STD_ULOGIC;
VHDL-93 package std_logic_1164 contains:
     SUBTYPE std_logic IS resolved std_ulogic;
During VHDL import references are resolved and the name of the subtype declaration is used instead of the name of the reference. EASE should keep the name of the reference even if it does not match (uppercase/lowercase) of the declaration.
2074 When propagating an instance port up multiple nets will be created 9.1.6 Problem only occured when connect using tags was selected.
2072 One/Two hot statemachine encoding always uses a bit_vector 9.1.6 When using a One/Two hot encoding the state type can be set to bit_vector, std_logic_vector, std_ulogic_vector or unsigned. The VHDL code generator always uses bit_vector.
2071 Not possible to process verification messages in batch mode 9.1.6 In batch mode it is not possible to retreive the verification messages using TCL.
2047 Incorrect VHDL type for a wire 9.1.5 When adding a wire starting in a VHDL block diagram at a Verilog component port which has a range, the VHDL type of the wire is set to std_logic instead of std_logic_vector.
2045 EASE can crash when creating a new primary unit after a library object identifier reset 9.1.5 When the object identifier of a library is reset, but not yet saved, the library storage is not yet present, so no new objects can be created.
2043 Context declaration loses use clauses on VHDL import 9.1.5 The use clauses are lost when the destination library for a context declaration is the same library the context has use clauses for.
2042 Context declaration can not be moved using drag&drop 9.1.5 A context declaration can only be moved to another library using the context menu but not by drag&
2040 Lint results filter no longer work properly after using column sort by clicking one of the column headers 9.1.5 When using filters on the lint results (e.g. to filter all lint warnings) and clicking one of the headers (e.g. to sort on severity) filtered items may appear again (and others may be hidden).
2039 Unable to create testbench/HDL Ware inside managed/imported library 9.1.4 When trying to create a testbench or HDL Ware or if you try to use a Core generator it is not possible to select a managed/imported library as target even if this library is writeable.
2038 HDLWare generation fails when project uses a env. variable in its project path 9.1.4 TCL doesn't expand environment variables used in the project path
2036 Fuzzy parser does not detect end of package correctly 9.1.4 If a package contains a package instantiation statement it is possible the end of the package is treated as the end of the package instantiation.
2031 EASE crashes when editing a single wire in Verilog module 9.1.3 Only crashes when trying to edit properties of a virtual net in Verilog.
2030 Incorrect VHDL-1101 error message 9.1.3 VHDL parser would issue (incorrect) message in function calls using named associations with a file type.
2025 Modelsim error reporting improved 9.1.2 Some Modelsim errors have a changed format (string '(suppressible)' after the string '** Error') failing the error recognition.
2022 VHDL linter does not report all Misc12 (signal has neither asynchrous reset nor initial value) cases 9.1.2 Code like:
mySignal <= (others=>'0') when myReset else myValue;
failed to issue the message.
2020 When moving block up/down using arrow keys it sometimes moves to the left/right as well 9.1.2 Problem occurs when center of block is not on grid position.
2019 VHDL linter CP 14 false positive 9.1.2 When a package instantiation declaration is present in architecture the reference finder is not properly restored after the package instantiation.
2018 Find (F12) on search results behaves weird when used from inside detached diagram with own search results 9.1.2 The F12 shortcut is declared global. Using F12 when searching inside (detached) editor does not do what you expect or want.
2015 Too many signals on sensitivity list for master FSM 9.1.1 Signals in the slave of a master/slave FSM, which were only in slave were also added to sensitivity list for master FSM.
2010 'Delete code ?' question asked twice 9.1.1 When adding a new action to an FSM statemachine, typing some hdl code and then select an existing label, the question: 'No label defined for current HDL code. Delete code?' is asked twice.
2009 Incorrect label for component using direct instantiations 9.1.1 When direct instantiations are used in the project and the component does not use the default architecture both the component label and tooltip still refer to the default label.
2008 EASE will crash when doing an unselect in the FSM labels dialog. 9.1.1 An unselect of unnamed label of an action in the FSM Labels dialog followed by an OK will cause EASE to crash.
2007 Missing use clause 9.1.1 No library and use clause generated for instantiation inside generate statement
2004 VHDL linter Misc2 (latch detected) false positive 9.1.1 VHDL linter reports Misc2 for conditional signal assignment inside clocked process.
2003 Ease crashes after undo/redo of linked library delete 9.1.1 When a linked library is created from an undo/redo transaction the internal data is incorrect
2002 Delete Top Level entity 9.1.1 Import subtree allows import of (second) Top level entity but it is impossible to delete this second Top level entity
2001 When assigning user defined name to net move its label to the default position 9.1.1 When moving ports (or blocks containing ports) the labels of the connected nets are not always moved as well. Usually this will be noted and adjusted by the user, but when the net is virtual no net label is visible (and so it is highly unlikely that the user will adjust its position).
2000 Ease crashes when undo/redo action is initiated during wiring 9.1.1 As title
1999 Allow specification of multiple file name extensions for a language (VHDL) 9.1.1 It should be possible to specify file filters in dialogs should support both .vhd and .vhdl extensions.
1998 Moving ports to opposite side of block gives strange results 9.1.1 When moving a list of ports from one side of a block to the opposite side this will lead to weird results.
1997 Meta generic label move not persistent 9.1.1 After moving the label of a meta generic, the label will move back to its original position the first time the component is synchronized.
1996 Selected objects are moved after moving sheet (using SHIFT + mouse wheel) 9.1.1 In some cases the selected objects are moved after moving the sheet using SHIFT + mouse wheel.
1995 When adding use clause it is not selected 9.1.1 When adding a use clause to an object the newly created use clause (using the Insert button in the dialog) is not selected in the list of defined use clauses (at the top of the dialog). This means you have to select it first if you want to move it to another place in the list.
1993 Improved search in instantiate dialog 9.1.1 Added options to search gadget
- case sensitive / case insensitive
- whole word
1992 Customizable label for meta generic 9.1.1 Label for meta generic is now "3 generics". It would be better if it would only show "3". Maybe label properties "name" and "type" can be used to not show the "type" part of the label.
1991 Crash after moving objects 9.1.1 Ease will crash after moving objects in a block diagram in specific situations
1990 If an external editor is specified show HDL preview in external editor 9.1.1 When external editor is specified create temporary file in ease.tmp directory.
1989 When moving block ports using keyboard they will move around corner based on mouse position 9.1.1 Algorithm used mouse position to determine if we needed to move 'around the corner'. When translating using keyboard we now use relative position of first selected object.
1967 VHDL import changes order of declarations 9.1.1 When importing VHDL the declarations are separated in two parts:
- Declarations before signals
- Declarations after signals

Problem is that the declaration these sections are filled based on the type of the declaration and not if the declaration was before the first signal declaration or after the first signal declaration. This causes problems (e.g. in code generated by Xilinx core generator).
1851 Easy way to revert a unit to an older version 9.1.1 To revert a unit you need to check it out, select an older version and do a checkin again. Would be nice to perform this in one action.
1795 Support for attribute declarations and attribute specifications 9.1.1 Easier way to deal with attribute declarations and attribute specifications.
1591 Specific comment to document generic actual value. 9.1.1 Sometimes it is useful/necessary to add additional comment to the actual value of generic.
1535 VHDL library clauses needed for direct instantiations not imported 9.1.1 When importing VHDL as text (architecture HDL files) and the VHDL contains direct instantiations, no use clauses and library clauses are generated.
1395 Diagram not updated after change to virtual record 9.1.1 When changing a virtual record type (e.g. toggling the direction), while inside an unmodified diagram that uses this virtual record, incorrect code may be generated. Things will automatically be repaired when any change is made to the diagram.
597 Move ports round a corner 9.1.1 If a number of ports are moved round the corner of the drawn block, they do not go round the corner but are put on top of each other in the corner.
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