Problems fixed in IO Checker 3.4

Improved Xilinx configuration files 3.4.4 Improved Xilinx configuration files of Artix 7, Kintex 7, Spartan 7 and Virtex 7
1986 Not all POWER_PINS entries in Allegro packager pstchip.dat file are imported 3.4.4 When the Allegro pstchip.dat file contains multiple POWER_PINS entries for a chip only the last entry will be imported.
1985 Crash when importing Allegro packager pstchip.dat file 3.4.4 When importing the Allegro packager pstchip.dat file while the PCB unconnected net property was set to an emtpy string a crash would occur when parsing a line containing a NC_PINS definition.
1956 Wire both $LOCATION and LOCATION components in Cadence Allegro 3.4.4 In some sheets the FPGA components uses both LOCATION and $LOCATION reference designator.
1959 IO Checker unable to generate rules 3.4.3 IO Checker is unable to find rules the first time an project is created from the Altium Extension. Second time you start the rules dialog, from the UI, it can.
Microsemi devices 3.4.3 Added Polar family
Xilinx devices 3.4.3 Device updates for Spartan7, VirtexupHBM and ZynqupRFSoc
Altera devices 3.4.3 Device updates for MAX10, Stratix10 and Arria10
1945 Adding a new signal in an empty HDL view fails 3.4.2 IO Checker could crash when adding a new signal to an empty view.
1941 Signals in the HDL view sorted incorrectly 3.4.2 After a save as the elements of HDL vectored signals are sorted purely alphabetical (thus a<<1>.>, a<11>.,.. a<2>. Instead of alpha numerical inside the vector. This makes drag & drop more difficult.
Device update 3.4.2 New Xilinx Spartan 7 devices
1905 Matching data is not reset when PCB data is removed 3.4.1 The matching rule data is not updated (eg removed) when the PCB data is removed.
1899 Show a combined pullup/pulldown resistor 3.4.1 Some FPGA pins have both a pullup/pulldown resistor (voltage divider)
1897 Support a CSV import based on signal name and optional direction + IO Type 3.4.1 Support an import like the VHDL/Verilog for a CSV file. This would allow a simple starting point to assign pad names to signals and/or direction/IO types.
1896 Microsemi report by name file has an extra column 3.4.1 The report_by_name file (Libero V11.7) for an Igloo2 M2GL06FG484 has a Bank column before the I/O Std column.
1892 Not all Xilinx IO standards are correctly set to be LVDS type 3.4.1 For a number of IO standards the IO type was not set to be LVDS type. This implies that no LVDS pair P/N check is performed for pins using this standard.
1891 HDL Generator dialog is not sticky 3.4.1 When the dialog is invoked a second time in the same session all previous selected options and values are lost.
1890 User specified power voltage ignored 3.4.1 A user defined voltage can be specified for a power pin. However if the voltage of this power pin is determined from the netlist, the user specified value is ignored.
1883 Recurring messages about missing pads in the pin report file 3.4.1 A pin file of Lattice or Microsemi can be incomplete. Each time that Pin view is rebuild a message is printed for each missing pin.
1882 To many and unclear messages in the schematic wiring interface 3.4.1 When running the schematic interface for Allegro or Altium based on the pin file and this file is incomplete 5 messages are generated for each missing pin. Incomplete pin report files are common for Lattice and Microsemi so we should reduce and improve error messaging.
1879 Signalview find widget finds hidden items 3.4.1 Rows which are hidden are still used by the search widget.
1854 User defined power rule not usable 3.4.1 It is not possible to define and use a user power rule if a user has pcb power signal names which match (incorrectly) with a power rule in the install power_rules.xml file. The user rules should be loaded before the installation rules.
1848 Add more info to 'Help about' dialog 3.4.1 From the 'Help about' dialog it should be possible to check if new versions/revisions are available. Also it should be possible to open a browser on a page showing the changes made in these new versions/revisions.
1823 Filter to just view power and/or ground pins 3.4.1 It is not possible to only show power and/or ground pins.
1720 A signal view export option 3.4.1 Add an CSV export with selectable columns.
1626 Use derived name of PCB signal in the matching rules 3.4.1 Use the derived PCB name (after the => in the signalview) in the rules checking
1240 Legenda for Device View 3.4.1 Explain symbols and colors in the device view
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