An expression calculates a value from a set of operators and operands.

Syntax:

operand | operator operand | operand operator operand

Description:

An expression produce a result from a set of operators and operands.

The operand is:

• number
• net name
• variable name of register data type
• bit-select of net name or variable name of type: reg, integer or time (e.g. Name[10])
• part-select of net name or variable name of type: reg, integer or time (e.g. Name[16:8])
• memory element (e.g. Memory[3])
• function call

The indices for a bit-select or memory element may be an expression. The indices for a part-select must be a constant expression.

In Verilog-2001 the part-select can be of the form:

[base_expr offset: width_expr]
offset = + | -

The base expression may vary during simulation run time. The width expression must be a constant. The offset direction indicates if the width expression is added to or subtracted from the base expression.

Example:

A+B
reg [3:0] Index = 3;
BitSelect[Index]
PartSelect[34:28]
Memory[Index]
reg [1:0] PartS;
reg [7:0] Vector = 8'b10101110
PartS = Vector [3 :+ 2]                // Verilog-2001: Vector[4:3] is assigned to PartS. PartS = 01
reg [31:0] Vector
reg [63:0] DWord;
integer Sel = 2;
if (Sel > 0 && Sel < 8)
  DWord[8 * Sel -: 8] = Vector[7:0];   // Verilog-2001: Vector[7:0] is assigned to DWord[16:9].  

Notes:

• An X is returned when the indices are out of range.
• A bit- or part-select of an array word is not permitted in Verilog-1995. Verilog-2001 allows a bit- or part-select of an array word.

See also:

Operator