A module is the basic unit in Verilog and represents hardware components by describing the interface and design behaviour.

Syntax:

module_word module_name [ ( port_list ) ];
  module_items;
endmodule 

module_word = module | macromodule

Description:

Modules can be used to represent hardware components by describing the hardware interface and behaviour, or can be used to declare parameters, tasks and functions that are used elsewhere in the design.

The keyword macromodule is a synonym for module. Some EDA tools compile macromodules differently from modules, for example by flattening macromodule hierarchy. This might make simulation more efficient in terms of speed or memory.

Example:

module Mod1(A, B, C);
  input A, B;
  ouput C;
  assign C = A & B;
endmodule

Notes:

• The same keyword, endmodule, is used at the end of both modules and macromodules.

See also:

Instantiation, Port declaration