The ports of a module declare the interface of the module.

Syntax:

port_direction [ port_size ] port_name, port_name, ...;
port_direction data_type [ port_size ] port_name, port_name, ...;

port_direction = input | output | inout

Description:

The module ports model the pins of hardware components. The port declaration specifies the port direction of the ports listed in the module declaration.

Verilog requires that signals connected to the input or output of a module have two declarations: the port direction, and the data type of the signal. If no data type is declared, it is implicity declared as a wire with the same size as the corresponding port.

In Verilog-2001 the two declarations, direction and data type, may be combined in one statement.

The port declaration and the port list in the module declaration may even be combined in one statement in Verilog-2001. This combination is known as the ANSI-style. The syntax for this combination is:

module module_name ( port_direction data_type [ port_size ] port _name, port_name, ...);

Example:

input Clk;
output [7:0] Q;
input wire Clk;                              // Verilog-2001
output reg [7:0] Q;                          // Verilog-2001

module Cnt (output reg [7:0] Q,
            input wire Clk, Reset, Enable,
            input wire [7:0] D );            // Verilog-2001 ANSI-style

See also:

Module