The data types of the operands are used to determine if signed or unsigned arithmetic should be performed when doing integer math operations. Both operands must be signed to perform signed arithmetic. In Verilog-1995, the integer data type is signed, and the reg and net data types are unsigned.

Verilog-2001 adds five enhancements to provide greater signed arithmetic capability:

• Declaring reg data types, net data types, ports and functions as signed.
  The keyword signed is used to declare net data types, reg data types, ports, and functions as signed types.
• Declaring integer numbers in any radix as signed.
  Verilog-2001 adds an additional specifier, the character s or S. This specifier can be combined with the radix specifier to indicate that the literal number is a signed value.
• Converting operands from unsigned to signed and vice-versa.
  The system functions $signed() and $unsigned() evaluate the input expression and return a value with the same size and value of the input expression and the type defined by the function.
• New arithmetic shift operators: <<< and >>>.
  The right shift arithmetic operator shifts the left operand to the right by the number of bit positions given by the right operand. The vacated bit positions are filled with zeros if the result type is unsigned. If the result type is signed, the vacated bit positions are filled with the value of the most-significant bit of the left operand.
  The left shift arithmetic operator shifts the left operand to the left by the number of bit positions given by the right operand. The vacated bit positions are filled with zeros.

Example:

reg signed [7:0] A;
wire signed [7:0] B;
input signed [15:0] C;
function signed [15:0] func1;
16'shCA93                           // 16-bit signed hex value
Result = $signed(D) / 2;            // signed arithmetic
reg signed [7:0] E = 8'b10100011
E >>> 3                             // arithmetic shift yields 8'b11110100 

See also:

Number, Operator