An architecture defines the internal organization or operation, i.e. describes the behaviour, data flow, or structure, of an associated entity.

Syntax:

architecture architecture_name of entity_name is
  [ architecture_declarations ]
begin 
  concurrent_statements
end [ architecture ] [ architecture_name ]; 

Description:

An architecture defines the internal view of a block of hardware, i.e. the functionality, behaviour or structure of the hardware. An architecture is assigned to an entity which defines the interface.

An entity can have multiple alternative architectures assigned to it. All the architectures assigned to the same entity must have different names, but architectures assigned to different entities can have the same name.

Example:

architecture Test of TbDff is 
  signal Clk, D, Q: std_logic := '0'; 
  component Dff 
    port(Clk, D: in std_logic; Q: out std_logic); 
  end component; 
begin 
  uut : Dff port map (Clk => Clk, D => D, Q => Q);
  Clk <= not (Clk) after 25 ns;
  stimulus : process
  begin
    wait for 50 ns;
	D <= '1';
    wait for 100 ns;
	D <= '0';
    wait for 50 ns;
  end process stimulus;
end Test; 

Notes:

• An architecture may not be used without an entity.
• All declarations defined in an entity are fully visible and accessible within each architecture assigned to this entity.

See also:

Concurrent statement, Configuration, Entity