An entity defines the interface between a design and the outside world.

Syntax:

entity entity_name is 
  [ generic ( generic_list ); ] 
  [ port ( port_list ); ]
  [ entity_declarations ]
[ begin
  concurrent_statements ]
end [ entity ] [ entity_name ]; 

Description:

An entity is used in combination with an architecture. Together they describe the behaviour or structure of an hierarchical block of hardware (a design entity). The architecture can be assigned to one entity only but one entity may be assigned to multiple architectures.

The entity declares the design name. In addition, it defines generics which provide static information (like timing parameters or bus width) to a design, and ports which provide communication channels between the design and its environment.

The entity declaration may be preceded by the library and use clauses. This way all declarations defined in a package will be visible for the entity and all architectures assigned to it.

Example:

library ieee;
use ieee.std_logic_1164.all;
  
entity BCD_Decoder is
  generic (Size: integer := 4);
  port (BCD: in std_logic_vector(2 downto 0);
        Enable: in std_logic;
        LED: out std_ulogic_vector (Size-1 downto 0)); 
  constant Zero: std_ulogic_vector(Size-1 downto 0) := (others => '0');
begin
  assert (BCD /= "111") report "BCD is 7" severity note;
end BCD_Decoder;

Notes:

• The LRM uses the name design entity for a complete specification of the design, i.e. both its interface (entity unit) and behaviour or structure (architecture unit). Therefore entity and design entity are not the same concepts!
• It is possible to write an entity without any generics, ports and statements. In fact this is used in constructing testbenches.

See also:

Architecture, Generic, Instantiation, Port