A value, function, type, range, signal, or constant that may be associated with one or more types, objects, subprograms, etc.

Syntax:

attribute attribute_name: type_name;                                                -- declaration 
attribute attribute_name of object_name [ signature ] : object_class is expression; -- specification 

signature = [ type_name, ... ] return type_name
object_class = signal | type | function | architecture { etc } 

Description:

A user-defined attribute is used to attach arbitrary information to a specific part of a VHDL description for use by downstream tools (e.g. synthesis, simulation, etc.). Any attribute not recognized by a particular tool is ignored.

An attribute specification must be in the region in which the object name is declared. Attributes of an entity, architecture, configuration or package must be specified inside that region. Neither attribute declaration nor specification is allowed in a package body.

A user-defined attribute can be of any VHDL type, except for an access type, file type, and any complex type with elements of any of these two types.

Example:

attribute pin_number: positive;
attribute pin_number of Clk: signal is 1;

Note:

• Common attributes can be declared for objects of different classes using one construct: group. See Group for details.

See also:

Attributes (predefined), Group