Name |
LRM §6. |
Any VHDL item is identified by its name.
identifier -- simple name \extended_identifier\ "operator" attribute_name name.name. ... -- selected name name(range) -- slice name name(expression, ...) -- indexed name
Any declaration that introduces a named item defines an identifier which enables reference to such an item by using this identifier. However, it is not always possible to refer to an item or part of it by using just its identifier. More general form of reference to items is by a name. Names can also indicate objects of the access type, elements of the composite type, parts of the composite object or unit attributes which have an identifier in their declaration. The name can have any of the following forms:
A name consists of letters, digits and underscores. The extended_identifier has to be used when the first character is not a letter, the last character is an underscore, or when the identifier has two adjacent underscores.
ABC_66 -- simple name \4A*@_\ -- extended identifier "+" -- operator Clk'Event -- attribute name IEEE.std_logic_1164."nor" -- selected name SignalSlice(12 to 15) -- slice name DataSignal(5) -- indexed name
Array, Attributes (predefined), Expression, Operator, Range, Record