A package contains common definitions that can be shared across a VHDL design or even multiple designs.

Syntax:

package package_name is 
  package_declarations
end [ package ] [ package_name ]; 

Description:

The package is a unit that groups various declarations, which can be shared among several designs. Packages are stored in libraries. A package is split into a package declaration (mandatory) and a  package body (optional).

The purpose of a package is to declare shareable types, subtypes, constants, signals, files, aliases, component, attributes and groups. Once a package is defined, it can be used in multiple independent designs.

Items declared in a package declaration are visible in other design units if the use clause is applied.

Example:

library IEEE; 
use IEEE.std_logic_1164.all; 
package Utils is 
  constant Size: positive; 
  subtype Vec8 is std_logic_vector(7 downto 0);
  function Parity (V: Vec8) return std_logic; 
end Utils; 

Notes:

• A package declaration may contain a subprogram (function or procedure) declaration; the subprogram body is not allowed here and must appear in the package body.
• A package body must accompany a package declaration if the declaration contains subprogram declarations or deferred constants.
• Only definitions placed in the package declaration are visible outside the package.

See also:

Function, Package body, Procedure, Type, Use