Achieves direct visibility of declarations that are visible by selection.

Syntax:

use library_name[ .package_name ].item_name; 

Description:

The use clause makes names defined in a library directly visible within another region of the VHDL code. The use clause is typically written at the top of an entity (giving access to common definitions from a package) or at the top of a configuration (giving access to the entities and architectures in a library).

The item_name specified in the use clause, specifies the item that will be visible. If a designer wants to have all declarations in a package visible, then the item_name should be substituted by the reserved word all.

The use clause is valid for the design unit immediately following it and for all secondary design units assigned to this design unit (if it is a primary design unit). If a file contains more than one design unit, then each design unit must have its own use clauses. In other words, use clauses are not global within a file.

Example:

use IEEE.std_logic_1164.all; 
use WORK.ArithOp.Add;
use WORK.all

See also:

Library, Package