A port map is used to define the interconnection between instances.

Syntax:

port map ( [ port_name => ] expression, ... )

Description:

A port map maps signals in an architecture to ports on an instance within that architecture. Port maps can also appear in a block or in a configuration.

The connections can be listed via positional association or via named association.

Within an instance, the port names are ports on the component or entity being instanced, the expressions are signals visible in the architecture containing the instance. Within a configuration, the port names are ports on the entity, the expressions are ports on the component.

The elements of an array port can be connected individually when using named association.

Ports may be left unconnected using the keyword open.

Example:

architecture Structure of Top is
  component CompA
    generic (...);
    port (Clk, Rst: in std_logic;
          D: in std_logic_vector(3 downto 0);
          Rd : out std_logic;
          Q: out std_logic_vector(3 downto 0));
  end component;
begin
  u1: CompA generic map(...)
            port map(Clock, Reset, DIn, QOut);
  u2: CompA generic map(...)
            port map(Clk => Clock,
                     Rst => Reset,
                     D => DIn,
                     Rd => open,
                     Q(0) => QOut1,
                     Q(3 downto 1) => QOut2);
end Structure;

Notes:

• A conversion function in a port map must have one parameter only.

See also:

Block, Configuration, Generic map, Instantiation, Port