A channel for dynamic communication between a block and its environment.

Syntax:

port ( port_name, ... : [ mode ] data_type [ := Expression ] );

mode = in | out | inout | buffer | linkage

Description:

A port represents a pin or a related group of pins on a hardware component.

A port is, technically, a signal.

The five different modes have the following definitions:

• in input port. This port can only be read. It is not allowed to assign a value to it.
• out output port. This port can only be assigned. It is not allowed to read from it.
• inout bi-directional port. Both assignments to such a port and reading from it are allowed.
• buffer output port with read capability. It differs from inout in that it can be updated by at most one source, whereas inout can be updated by zero or more sources.
• linkage. The value of the port may be read or updated, but only by appearing as an actual corresponding to an interface object of mode linkage.

Example:

port (Clk, Rst: in std_logic;
      D: in std_logic_vector(3 downto 0);
      Status: out std_logic;
      Q: buffer std_logic_vector(3 downto 0);

Note:

• Port declarations are signal declarations and port signals need not to be re-declared.

See also:

Block, Component, Entity, Generic, Port map