Signal is an object with a past history of values. A signal may have multiple drivers, each with a current value and projected future values. The term signal refers to objects declared by signal declarations and port declarations.

Syntax:

signal signal_name : data_type [ kind ] [ := expression ]; 

kind = register | bus   -- guarded signal

Description:

A signal represents an electrical connection, wire or bus. Signals are used for communication between processes.

Signals can be explicitly declared in the declarative part of:

• package declaration: signals declared in a package are visible in all design entities using the package (through the use clause).
• architecture: such signals are visible inside the architecture only.
• block: the scope of such signals is limited to the block itself.
• subprogram (function and procedure): the scope of such signals it limited to the subprogram itself.

A port declaration in an entity is an implicit signal declaration. A signal declared this way is visible in all architectures assigned to that entity.

A signal can get a default value in its declaration. If the signal declaration does not contain a default value, then the default value of the signal is the left bound of the specified type. The default value is ignored for synthesis; use an explicit reset to get both the VHDL and the synthesized hardware into the same known state.

A signal declared with a kind statement can have individual drivers disconnected from the resolution function. This signal must be of a resolved type. A register type signal with no drivers connected retains its previous value. The bus type signal relies on the resolution function to supply a "no-drive" value. Most synthesis tools ignore resolution functions.

Example:

signal S1, S2: std_logic_vector(7 downto 0);
signal S3: std_ulogic := '0'; 

See also:

Block, Signal assignment