A signal assignment statement modifies the target signal

Syntax:

[ label: ] target_signal <= [ options ] expression [ after time_expression ] [ when condition ]; 

options = guarded { in a guarded block } | transport | reject time_expression inertial

Description:

A Signal assignment statement can appear inside a process (sequential statement) or directly in an architecture (concurrent statement). The target signal can be either a name (simple, selected, indexed, or slice) or an aggregate.

A signal assignment with no delay (or zero delay) will cause an event after delta delay, which means that the event happens only when all of the currently active processes have finished executing (i.e. after one simulation cycle).

The default delay mode (inertial) means that pulses shorter than the delay (or the reject period if specified) are ignored. Transport means that the assignment acts as a pure delay line.

VHDL'93 defines the keyword unaffected which indicates a choice where the signal is not given a new assignment. This is roughly equivalent to the use of the null statement within case (see Examples).

Example:

W <= A * B; 
X <= transport C after Delay;     
Y <= '0', '1' after 10 ns, '0' after 20 ns;
Z <= reject 2 ns inertial Inp after 10 ns;
P <= E1 when C1 else
     E2 when C2 else
     E3;
Q <= D when Enable = '1' else unaffected;

Note:

• Delays are usually ignored by synthesis tool.

See also:

Aggregate, Concurrent statement, Sequential statement, Signal, Variable assignment