A variable stores a value within a process.

Syntax:

variable variable_name : data_type [ := expression ]; 

Description:

A variable is an object that stores information local to the process and subprogram (procedures and functions) in which it is defined. A variable's values can be changed during simulation through the variable assignment statements.

A variable declaration includes one or more identifiers, a (sub)type indication and an optional initial value for the variable. A variable can be declared to be of any type or subtype available, either constrained or unconstrained.

Variables that are declared in processes are initialized with their default values at the start of the simulation. Variables declared in subprograms are initialized each time the subprogram is called.

The scope of variables is limited to the process or subprogram they are defined in. The only exception to this rule is a shared variable, which may be shared by multiple processes.

Although the LRM allows several processes to access a single shared variable it does not define what happens when two or more conflicting processes try to access the same variable at the same time. Such a situation may lead to unpredictable results and therefore should be avoided.

Example:

variable V, W: std_logic_vector(7 downto 0);
variable X: integer := 5;

Notes:

• Unlike signals, variables have neither history nor future, because according to its definition, each variable has only current value. No checking for the last event, time elapsed since the last event, previous value, etc. can be performed on variables.
• If a value of a variable is read before it is assigned in a clocked process then a register will be synthesized for this variable. A similar situation inside a combinatorial process may lead to generation of a latch.
• Variables declared in a subprogram are synthesized as combinatorial logic.

See also:

Signal, Variable assignment