Component |
LRM §4.5. |
A component declaration declares a virtual design entity interface that may be used in the component instantiation statement.
component component_name [ is ] [ generic ( generic_list ); ] [ port ( port_list ); ] end component [ component_name ];
A component represents an entity/architecture pair. It specifies a subsystem, which can be instantiated in another architecture leading to a hierarchical specification. Component instantiation is analogous to a chip in a socket in a board.
A component must be declared before it is instantiated.
The binding of a design entity to a given component may be delayed and may be placed either in the configuration specification or configuration declaration. For default configuration, the component name must match the name of the corresponding entity to be used in its place, and the entity name must be visible. Also generics and ports must match in name, mode and type.
The component can be defined in a package, design entity, architecture, or block declaration. If the component is declared in an architecture, it must be declared before the begin statement of the architecture. In such a case, the component can be used (instantiated) in the architecture only.
If a component is declared in a package, then such a component is visible in any architecture, which uses this package.
component Counter is
generic(N: integer);
port(Clk, Rst, En: in std_logic;
Q: out std_logic_vector(N-1 downto 0));
end component;