Documentation for implementation receiver.edgedet.rtl
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6 module edgedet (clk, d, d_neg, d_pos, resetn) ;
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8 input clk;
9 input d;
10 output d_neg;
11 reg d_neg;
12 output d_pos;
13 reg d_pos;
14 input resetn;
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16 reg d_old;
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18 always @(posedge clk or negedge resetn)
19 begin
20 if (~resetn)
21 begin
22 d_neg <= 1'b0;
23 d_pos <= 1'b0;
24 d_old <= 1'b0;
25 end
26 else
27 begin
28 if (d && !d_old)
29 d_pos <= 1'b1;
30 else
31 d_pos <= 1'b0;
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33 if (!d && d_old)
34 d_neg <= 1'b1;
35 else
36 d_neg <= 1'b0;
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38 d_old <= d;
39 end
40 end
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42 endmodule
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