Generated by Ease for demo on Thu Jan 13 15:19:29 2022

Documentation for implementation receiver.edgedet.rtl

Contents Side Data Generated HDL
    1  ////////////////////////////////////////////////////////////////////////////////
    2  // Object        : Module receiver.edgedet
    3  // Last modified : Mon Nov 16 16:06:14 2020
    4  ////////////////////////////////////////////////////////////////////////////////
    5  
    6  module edgedet (clk, d, d_neg, d_pos, resetn) ;
    7  
    8    input      clk;
    9    input      d;
   10    output     d_neg;
   11    reg        d_neg;
   12    output     d_pos;
   13    reg        d_pos;
   14    input      resetn;
   15  
   16  reg d_old;
   17  
   18  always @(posedge clk or negedge resetn)
   19  begin
   20    if (~resetn)
   21    begin
   22      d_neg <= 1'b0;
   23      d_pos <= 1'b0;
   24      d_old <= 1'b0;
   25    end
   26    else               
   27    begin
   28      if (d && !d_old)
   29        d_pos <= 1'b1;
   30      else
   31        d_pos <= 1'b0;
   32        
   33      if (!d && d_old)
   34        d_neg <= 1'b1;
   35      else
   36        d_neg <= 1'b0;
   37        
   38      d_old <= d;        
   39    end
   40  end
   41  
   42  endmodule // edgedet
   43  
   44