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Index

Index for project uart (/home/willem/tmp/uart.ews)

• Project: uart
  • ieee.std_logic_1164.ALL
  • ieee.std_logic_unsigned.ALL
  • ieee.std_logic_arith.ALL
  • Package: std_logic_1164
  • Package: std_logic_arith
  • Package: std_logic_unsigned
  • Library: receiver
  • Entity: Toplevel
  • Architecture: structure
  • Module: edgedet
  • Implementation: rtl
  • Module: rec_fsm
  • Implementation: structure
  • Module: receiver
  • Implementation: structure
    • Instance: u0: rec_fsm : structure
    • Instance: u1: edgedet : rtl
    • Instance: u2: edgedet : rtl
    • Always Construct: sync
    • Always Construct: baudal
  • Library: uart
  • Entity: Toplevel
  • Architecture: a0
    • Instance: u0: uart_tb : test
  • Entity: clock_gen
  • Architecture: text
  • Entity: cntrl
  • Architecture: rtl
  • Entity: stim
  • Architecture: rtl
  • Entity: transmit
  • Architecture: fsm
  • Entity: transmitter
  • Architecture: structure
    • Instance: u0: transmit : fsm
    • Process: reg
    • Process: baudpr
    • Process: edgedet
  • Entity: uart
  • Architecture: structure
    • Instance: u0: transmitter : structure
    • Instance: u1: receiver : structure
    • Instance: u2: cntrl : rtl
    • Concurrent Statement: oe
  • Entity: uart_tb
  • Architecture: test
    • Instance: u1: clock_gen : text
    • Instance: u0: uart : structure
    • Instance: u3: stim : rtl

Hierarchy for the top-level object

• Entity uart_tb