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receiver

receiver

Documentation for implementation receiver.receiver.structure

    1  ////////////////////////////////////////////////////////////////////////////////
    2  // Object        : Module receiver.receiver
    3  // Last modified : Thu Apr 22 09:29:57 2021
    4  ////////////////////////////////////////////////////////////////////////////////
    5  
    6  module receiver (data, frame_err, nr_dbits, parity_en, parity_err, resetn, rx, 
    7    rxrdy, sclk, stop_2bit) ;
    8  
    9    parameter  dwidth = 8; // Data width parallel data
   10    output     [dwidth-1:0]data;
   11    output     frame_err;
   12    input      [1:0]nr_dbits;
   13    input      parity_en;
   14    output     parity_err;
   15    input      resetn;
   16    input      rx;
   17    output     rxrdy;
   18    input      sclk;
   19    input      stop_2bit;
   20    reg  rx_s;
   21    reg  rxclk;
   22    wire pos_rxclk;
   23    wire d_neg;
   24    reg  rx_i;
   25    reg [2:0] cnt;
   26  
   27    rec_fsm #(
   28      dwidth)  // dwidth
   29      u0(
   30        .data(data),
   31        .frame_err(frame_err),
   32        .nr_dbits(nr_dbits),
   33        .parity_en(parity_en),
   34        .parity_err(parity_err),
   35        .pos_rxclk(pos_rxclk),
   36        .resetn(resetn),
   37        .rx(rx_s),
   38        .rx_falling(d_neg),
   39        .rxrdy(rxrdy),
   40        .sclk(sclk),
   41        .stop_2bit(stop_2bit));
   42  
   43    edgedet
   44      u1(
   45        .clk(sclk),
   46        .d(rxclk),
   47        .d_neg(),
   48        .d_pos(pos_rxclk),
   49        .resetn(resetn));
   50  
   51    edgedet
   52      u2(
   53        .clk(sclk),
   54        .d(rx_s),
   55        .d_neg(d_neg),
   56        .d_pos(),
   57        .resetn(resetn));
   58  
   59    always @(posedge sclk or negedge resetn)
   60  
   61    begin : sync  // EASE/HDL sens.list
   62      if (~resetn)  
   63      begin
   64        rx_i <= 0;
   65        rx_s <= 0;
   66      end
   67      else
   68      begin
   69        rx_s <= rx_i;
   70        rx_i <= rx;
   71      end  
   72        
   73    end // sync
   74  
   75    always @(posedge sclk or resetn)
   76  
   77    begin : baudal  // EASE/HDL sens.list
   78      if (~resetn)
   79      begin
   80        rxclk <= 0;
   81        cnt   <= 0;
   82      end
   83      else
   84      begin
   85        if (cnt == 0)
   86          rxclk <= !rxclk;
   87        if (cnt == 7)
   88          cnt <= 0;
   89        else
   90          cnt <= cnt + 1;
   91      end    
   92    end // baudal
   93  
   94  endmodule // receiver
   95  
   96