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1 -------------------------------------------------------------------------------- 2 -- Object : Entity uart.clock_gen 3 -- Last modified : Mon Nov 16 16:06:14 2020 4 -------------------------------------------------------------------------------- 5 6 library ieee; 7 use ieee.std_logic_1164.all; 8 use ieee.std_logic_unsigned.all; 9 use ieee.std_logic_arith.all; 10 11 entity clock_gen is 12 generic( 13 Period : time := 50 ns); 14 port ( 15 clk : out std_logic); 16 end entity clock_gen; 17 18