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Documentation for entity uart.cntrl

    1  --------------------------------------------------------------------------------
    2  -- Object        : Entity uart.cntrl
    3  -- Last modified : Thu Jan 13 15:17:39 2022
    4  --------------------------------------------------------------------------------
    5  
    6  library ieee;
    7  use ieee.std_logic_1164.all;
    8  use ieee.std_logic_unsigned.all;
    9  use ieee.std_logic_arith.all;
   10  
   11  entity cntrl is
   12    generic(
   13      dwidth : natural := 8); -- Data width parallel data
   14    port (
   15      addr      : in     std_logic_vector(1 downto 0);
   16      csn       : in     std_logic;
   17      data      : in     std_logic_vector(dwidth-1 downto 0);
   18      nr_dbits  : out    std_logic_vector(1 downto 0);
   19      parity_en : out    std_logic;
   20      resetn    : in     std_logic;
   21      sclk      : in     std_logic;
   22      stop_2bit : out    std_logic;
   23      wr        : in     std_logic);
   24  end entity cntrl;
   25  
   26