Generated by Ease for demo on Thu Jan 13 15:19:29 2022

Documentation for entity uart.stim

Contents Side Data Generated HDL
    1  --------------------------------------------------------------------------------
    2  -- Object        : Entity uart.stim
    3  -- Last modified : Mon Nov 16 16:06:14 2020
    4  --------------------------------------------------------------------------------
    5  
    6  library ieee;
    7  use ieee.std_logic_1164.all;
    8  use ieee.std_logic_unsigned.all;
    9  use ieee.std_logic_arith.all;
   10  
   11  entity stim is
   12    generic(
   13      dwidth : Natural := 8;
   14      Period : time := 50 ns);
   15    port (
   16      addr       : inout  std_logic_vector(1 downto 0);
   17      csn        : inout  std_logic;
   18      data       : inout  std_logic_vector(dwidth-1 downto 0);
   19      frame_err  : in     std_logic;
   20      parity_err : in     std_logic;
   21      rd         : inout  std_logic;
   22      resetn     : inout  std_logic;
   23      rx         : inout  std_logic;
   24      rxrdy      : in     std_logic;
   25      sclk       : in     std_logic;
   26      tx         : in     std_logic;
   27      txrdy      : in     std_logic;
   28      wr         : inout  std_logic);
   29  end entity stim;
   30  
   31