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transmitter

Documentation for architecture uart.transmitter.structure

    1  --------------------------------------------------------------------------------
    2  -- Object        : Architecture uart.transmitter.structure
    3  -- Last modified : Thu Jan 13 15:18:43 2022
    4  --------------------------------------------------------------------------------
    5  
    6  architecture structure of transmitter is
    7  
    8    signal cnt       : integer range 0 to 7;
    9    signal tx_clk    : std_logic;
   10    signal neg_txclk : std_logic;
   11    signal ld        : std_logic;
   12    signal d         : std_logic_vector(dwidth-1 downto 0);
   13    signal tx_clk_o  : std_logic;
   14  
   15    component transmit
   16      generic(
   17        dwidth : natural := 8);
   18      port (
   19        d         : in     std_logic_vector(dwidth-1 downto 0);
   20        ld        : in     std_logic;
   21        neg_txclk : in     std_logic;
   22        nr_dbits  : in     std_logic_vector(1 downto 0);
   23        parity_en : in     std_logic;
   24        resetn    : in     std_logic;
   25        sclk      : in     std_logic;
   26        stop_2bit : in     std_logic;
   27        tx        : out    std_logic;
   28        txrdy     : out    std_logic);
   29    end component transmit;
   30  
   31  begin
   32  
   33    u0: transmit
   34      generic map(
   35        dwidth => dwidth)
   36      port map(
   37        d         => d,
   38        ld        => ld,
   39        neg_txclk => neg_txclk,
   40        nr_dbits  => nr_dbits,
   41        parity_en => parity_en,
   42        resetn    => resetn,
   43        sclk      => sclk,
   44        stop_2bit => stop_2bit,
   45        tx        => tx,
   46        txrdy     => txrdy);
   47  
   48  
   49    reg: process (resetn, sclk) is        -- EASE/HDL sens.list
   50    begin
   51      if resetn = '0' then
   52        d  <= (others => '0');
   53        ld <= '0';       
   54      elsif rising_edge (sclk) then
   55        if csn = '0' and wr = '1' and addr = "00" then
   56          d <= data; 
   57          ld <= '1' after 10 ns, '0' after 20 ns;
   58      else
   59        ld <= '0';
   60        end if;
   61      end if;
   62    end process reg ;
   63  
   64    baudpr: process (sclk) is     -- EASE/HDL sens.list
   65    begin
   66      if resetn = '0' then
   67        tx_clk <= '0';
   68        cnt   <= 0;
   69      elsif rising_edge (sclk) then
   70        if cnt = 0 then
   71          tx_clk <= not tx_clk;
   72        end if;
   73        if cnt = 7 then
   74          cnt <= 0;
   75        else
   76          cnt <= cnt + 1;
   77        end if;
   78      end if;
   79    end process baudpr ;
   80  
   81    edgedet: process (tx_clk, resetn, sclk) is        -- EASE/HDL sens.list
   82    begin
   83      if resetn = '0' then
   84        neg_txclk <= '0';
   85        tx_clk_o  <= '0';
   86      elsif rising_edge (sclk) then
   87        if tx_clk = '0' and tx_clk_o = '1' then
   88          neg_txclk <= '1';
   89        else
   90          neg_txclk <= '0';
   91        end if;
   92        tx_clk_o <= tx_clk;
   93      end if;
   94    end process edgedet ;
   95  end architecture structure ; -- of transmitter
   96  
   97