Generated by Ease for demo on Thu Jan 13 15:19:29 2022

Documentation for entity uart.uart

Contents Side Data Generated HDL
    1  --------------------------------------------------------------------------------
    2  -- Object        : Entity uart.uart
    3  -- Last modified : Thu Jan 13 15:17:45 2022
    4  --------------------------------------------------------------------------------
    5  
    6  library ieee;
    7  use ieee.std_logic_1164.all;
    8  use ieee.std_logic_unsigned.all;
    9  use ieee.std_logic_arith.all;
   10  
   11  entity uart is
   12    generic(
   13      dwidth : natural := 8); -- Data width parallel data
   14    port (
   15      addr       : in     std_logic_vector(1 downto 0);
   16      csn        : in     std_logic;
   17      data       : inout  std_logic_vector(dwidth-1 downto 0);
   18      frame_err  : out    std_logic;
   19      parity_err : out    std_logic;
   20      rd         : in     std_logic;
   21      resetn     : in     std_logic;
   22      rx         : in     std_logic;
   23      rxrdy      : out    std_logic;
   24      sclk       : in     std_logic;
   25      tx         : out    std_logic;
   26      txrdy      : out    std_logic;
   27      wr         : in     std_logic);
   28  end entity uart;
   29  
   30