Back

Index

uart

uart

Documentation for architecture uart.uart.structure

    1  --------------------------------------------------------------------------------
    2  -- Object        : Architecture uart.uart.structure
    3  -- Last modified : Thu Jan 13 15:17:45 2022
    4  --------------------------------------------------------------------------------
    5  
    6  library receiver;
    7  use receiver.receiver;
    8  
    9  architecture structure of uart is
   10  
   11    signal parity_en : std_logic;
   12    signal d_out     : std_logic_vector(dwidth-1 downto 0);
   13    signal d_in      : std_logic_vector(dwidth-1 downto 0);
   14    signal nr_dbits  : std_logic_vector(1 downto 0);
   15    signal stop_2bit : std_logic;
   16  
   17    component transmitter
   18      generic(
   19        dwidth : natural := 8); -- Data width parallel data
   20      port (
   21        addr      : in     std_logic_vector(1 downto 0);
   22        csn       : in     std_logic;
   23        data      : in     std_logic_vector(dwidth-1 downto 0);
   24        nr_dbits  : in     std_logic_vector(1 downto 0);
   25        parity_en : in     std_logic;
   26        resetn    : in     std_logic;
   27        sclk      : in     std_logic;
   28        stop_2bit : in     std_logic;
   29        tx        : out    std_logic;
   30        txrdy     : out    std_logic;
   31        wr        : in     std_logic);
   32    end component transmitter;
   33  
   34    component receiver
   35      generic(
   36        dwidth : natural := 8); -- Data width parallel data
   37      port (
   38        data       : out    std_logic_vector(dwidth-1 downto 0);
   39        frame_err  : out    std_logic;
   40        nr_dbits   : in     std_logic_vector(1 downto 0);
   41        parity_en  : in     std_logic;
   42        parity_err : out    std_logic;
   43        resetn     : in     std_logic;
   44        rx         : in     std_logic;
   45        rxrdy      : out    std_logic;
   46        sclk       : in     std_logic;
   47        stop_2bit  : in     std_logic);
   48    end component receiver;
   49  
   50    component cntrl
   51      generic(
   52        dwidth : natural := 8); -- Data width parallel data
   53      port (
   54        addr      : in     std_logic_vector(1 downto 0);
   55        csn       : in     std_logic;
   56        data      : in     std_logic_vector(dwidth-1 downto 0);
   57        nr_dbits  : out    std_logic_vector(1 downto 0);
   58        parity_en : out    std_logic;
   59        resetn    : in     std_logic;
   60        sclk      : in     std_logic;
   61        stop_2bit : out    std_logic;
   62        wr        : in     std_logic);
   63    end component cntrl;
   64  
   65  begin
   66  
   67    u0: transmitter
   68      generic map(
   69        dwidth => dwidth)
   70      port map(
   71        addr      => addr,
   72        csn       => csn,
   73        data      => d_in,
   74        nr_dbits  => nr_dbits,
   75        parity_en => parity_en,
   76        resetn    => resetn,
   77        sclk      => sclk,
   78        stop_2bit => stop_2bit,
   79        tx        => tx,
   80        txrdy     => txrdy,
   81        wr        => wr);
   82  
   83    u1: receiver
   84      generic map(
   85        dwidth => dwidth)
   86      port map(
   87        data       => d_out,
   88        frame_err  => frame_err,
   89        nr_dbits   => nr_dbits,
   90        parity_en  => parity_en,
   91        parity_err => parity_err,
   92        resetn     => resetn,
   93        rx         => rx,
   94        rxrdy      => rxrdy,
   95        sclk       => sclk,
   96        stop_2bit  => stop_2bit);
   97  
   98    u2: cntrl
   99      generic map(
  100        dwidth => dwidth)
  101      port map(
  102        addr      => addr,
  103        csn       => csn,
  104        data      => d_in,
  105        nr_dbits  => nr_dbits,
  106        parity_en => parity_en,
  107        resetn    => resetn,
  108        sclk      => sclk,
  109        stop_2bit => stop_2bit,
  110        wr        => wr);
  111  
  112  
  113  
  114    data <= d_out when rd = '1' else (others => 'Z');
  115    d_in <= data after 5 ns;--, "000000" after 10 ns;
  116  end architecture structure ; -- of uart
  117  
  118