Documentation for architecture uart.uart_tb.test
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6 architecture test of uart_tb is
7
8 signal resetn : std_logic;
9 signal addr : std_logic_vector(1 downto 0);
10 signal csn : std_logic;
11 signal data : std_logic_vector(dwidth-1 downto 0);
12 signal rd : std_logic;
13 signal wr : std_logic;
14 signal rx : std_logic;
15 signal rxrdy : std_logic;
16 signal frame_err : std_logic;
17 signal parity_err : std_logic;
18 signal txrdy : std_logic;
19 signal tx : std_logic;
20 signal clk : std_logic;
21
22 component clock_gen
23 generic(
24 Period : time := 50 ns);
25 port (
26 clk : out std_logic);
27 end component clock_gen;
28
29 component uart
30 generic(
31 dwidth : natural := 8);
32 port (
33 addr : in std_logic_vector(1 downto 0);
34 csn : in std_logic;
35 data : inout std_logic_vector(dwidth-1 downto 0);
36 frame_err : out std_logic;
37 parity_err : out std_logic;
38 rd : in std_logic;
39 resetn : in std_logic;
40 rx : in std_logic;
41 rxrdy : out std_logic;
42 sclk : in std_logic;
43 tx : out std_logic;
44 txrdy : out std_logic;
45 wr : in std_logic);
46 end component uart;
47
48 component stim
49 generic(
50 dwidth : Natural := 8;
51 Period : time := 50 ns);
52 port (
53 addr : inout std_logic_vector(1 downto 0);
54 csn : inout std_logic;
55 data : inout std_logic_vector(dwidth-1 downto 0);
56 frame_err : in std_logic;
57 parity_err : in std_logic;
58 rd : inout std_logic;
59 resetn : inout std_logic;
60 rx : inout std_logic;
61 rxrdy : in std_logic;
62 sclk : in std_logic;
63 tx : in std_logic;
64 txrdy : in std_logic;
65 wr : inout std_logic);
66 end component stim;
67
68 begin
69
70 u1: clock_gen
71 generic map(
72 Period => Period)
73 port map(
74 clk => clk);
75
76 u0: uart
77 generic map(
78 dwidth => dwidth)
79 port map(
80 addr => addr,
81 csn => csn,
82 data => data,
83 frame_err => frame_err,
84 parity_err => parity_err,
85 rd => rd,
86 resetn => resetn,
87 rx => rx,
88 rxrdy => rxrdy,
89 sclk => clk,
90 tx => tx,
91 txrdy => txrdy,
92 wr => wr);
93
94 u3: stim
95 generic map(
96 dwidth => dwidth,
97 Period => Period)
98 port map(
99 addr => addr,
100 csn => csn,
101 data => data,
102 frame_err => frame_err,
103 parity_err => parity_err,
104 rd => rd,
105 resetn => resetn,
106 rx => rx,
107 rxrdy => rxrdy,
108 sclk => clk,
109 tx => tx,
110 txrdy => txrdy,
111 wr => wr);
112
113 end architecture test ;
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115
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uart_tb