December 2022, HDL Works announces the release and
immediate availability of
EASE 9.4, the Graphical HDL Design tool.
EASE is the most intuitive Graphical HDL Design Entry tool in the industry. Providing the user with a better means of communication, documentation, design entry and modification for any HDL design targeted for FPGA or ASIC. With its four integrated editors (block diagram, state diagram, truth table and text editors) EASE offers a suitable design entry for every HDL requirement. It includes integration with the industry standard revision control system Subversion for real multi-user support.
Buttons with images and other graphical user interface elements will follow the scale size set in Windows and Linux. Font scaling is improved when moving the application window to a second screen with different scaling.
In the user options dialog, Application page, you can specify a font size increase, which will increase all font sizes for application text, for which you cannot select the font and size in the user options (like in menus, dialogs and tab labels).
Entity generics (when the VHDL mode is VHDL2008) can be set to ‘constant’, ‘type’, ‘function’ and ‘procedure’. Generics of type ‘type’ can be used to specify the port type in the port list.
The generic type ‘constant’ is the same as a generic without a type mark.
A generic of type ‘function’ or ‘procedure’ is used to instantiate a component which uses a function/procedure specified in an architecture or package. In the shown example 2 ports of type ‘type_t’ have been defined for which the actual type is determined in the entity instantiation. In the VHDL import the handing of declarations and statements in entity declarations has been improved.
Search & replace using regular expressions has been implemented for entity ports and diagram nets.
Nets which have an attribute specification show a small dot in the wires like is done for virtual nets. The virtual net marking and attribute specification is now also shown in the connect by-name-tags.
When copying ports using drag & drop it is now possible to directly connect the new port to the same net as the original port (by pressing both CTRL and ALT keys during drop).The following shortcuts are added:
The shortcut m (Verilog instantiate module) is now deprecated (use a,m instead).
The state machines were extended with a timer process in Ease 9.3. The timer is a count-down timer loaded with either integer values, constants or generics (of type natural / integer). When using constants or generics (with an expression) an underflow can occur when the calculated delay value is less than the minimum (1 or 2 depending on the state machine style).
The underflow would cause a simulation failure. Using the ‘Prevent timer underflow’ check box additional code is added to test for the underflow condition and to prevent errors.
Replaced font pixel sizes by ‘em’ sizes, for which the behaviour can be adjusted in
the CSS file and improved layout. Replaced deprecated use of the attribute ‘name’ in
HDL text with the ‘id’ attribute.
Added tables with the entity/module port and generics (parameters) to the entity pages.
EASE 9.4 is available now. Prices begin at € 5040 for a perpetual license. EASE can be downloaded and evaluated freely from the HDL Works website.
HDL Works develops and markets high-performance, intuitive tools for complex HDL design across a wide spectrum of applications. Its software products are available for Linux and Windows platforms. HDL Works currently holds BoardTrace, EASE, HDL Companion, IO Checker and Scriptum in its product portfolio. Headquartered in Ede, The Netherlands, HDL Works is privately held.HDL Works BV
ConnTrace, EASE, HDL Companion, IO Checker and Scriptum are trademarks of HDL Works.
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