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HDL Works
HDL Works has three products for HDL development and two for verification in FPGA / PCB design. They all offer the novice and experienced HDL designers a flexible way to manage and develop their HDL projects.
Visualize and verify connectivity between PCBs and large components (including configurable micro controllers and FPGAs) on connected PCB's.
Independent of netlist formats and connection style (backplanes, connectors and/or rear panels).
Includes connector mapping for VPX connectors.
Graphical HDL Design tool for VHDL and (System)Verilog.
Combines block diagrams, state diagrams, truth tables and HDL code.
Supports user defined types in packages, generate statements
The SWISS Army knife for every HDL Design Engineer
It will give you a complete overview of any VHDL or Verilog design in
seconds.
Features include verification, linting and HTML generation.
FPGA pin-out versus PCB pin assignment verification of user IO, power and ground pins using an intelligent rule engine.
Pin location and IO standard constraint creation from PCB netlist.
FPGA schematic capture symbol creation.
A text editor focused at VHDL and Verilog, using a Multiple Document Interface. (Free of charge)
Fujitsu FLDL netlist and FTDL test format translated into a VHDL or
Verilog netlist.
Including specific Fujitsu cell libraries like CG31 and CG51.
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