HDL WORKS PRESENTS IO CHECKER™ 5.1

February 2024, HDL Works announces the release and immediate availability of IO Checker 5.1,
the FPGA and PCB IO verification tool.

About IO Checker

IO Checker will verify that signal names used in the FPGA are connected to the appropriate signals on the PCB. Additionally it verifies the voltage values connected to the FPGA power and reference pins. IO Checker uses rules (based on regular expressions) to match the signals names in both the FPGA and PCB design environment. The rules can be generated automatically and be fine-tuned by the designer. The automated approach will often match 80% to 90% of all device pins.

The flexibility of IO Checker allows it to be used in any design flow and does not require any design methodology. The rules generator in combination with the sorted problem view allows engineers to validate a 1000+ pin device in half an hour.

What is new in IO Checker 5.1

User interface

Menu changes
The ‘Edit’ menu in the main menu bar changed into ‘Project‘. Menu items from the ‘Tools’ menu that change the project have been moved to the ‘Project’ menu.

Row filters in various views
The Pin view row filter and device view pin filter have been reorganized and have three distinct groups. All filters now have an ‘OK’ and ‘Cancel’ button at the bottom. Clicking outside of the filter will now cancel any changes you made after opening the filter. At the right of each filter button there is a ‘Clear filter’ button to remove all filters.

Pin view

A new functional group name ‘IO’ has been added and all pins of a device are now placed in one or more functional groups. Pins can belong to multiple groups. (Like Intel MAX10 JTAG or VREF pins, which can also be used a regular user IO.)

Device view

Changed visualization of control, JTAG and VREF pins in device view:

Use diamond instead of circle for control pins (filled circle if pin cannot be used as IO, open circle if it can be used as IO).
Use filled square for JTAG pins that cannot be used as IO, open square for pins that can also be used as IO.
Use filled triangle for VRef pins that cannot be used as IO, open triangle for pins that can also be used as IO.
Improved feedback if pins on alternate device do not match:

LVDS / non-LVDS
LVDS direction not the same
LVDS partner not the same
Clock capable vs not clock capable

The device view legend dialog is now modeless.

Wiring tool

A new wiring utility has been created to wire symbols in Cadence Allegro / SystemCapture and Altium Designer.
It is started from the 'Tools >> Wiring' tool menu.

The main advantages of the new wiring tool:

Wires multiple components
Change any signal name before use in wiring
Set different ports to use in Allegro wiring
Set signal direction
Selective import from FPGA pinlist or constraints
Import from CSV file for non FPGA components

This first release can wire symbols in Cadence Allegro / SystemCapture and Altium Designer.

PCB netlist formats

Support for compressed Cadence packager pstcmdb.dat files. Support for the Allegro System Capture compressed ‘pstedb.cdsz’ format.

CSV export

The CSV Pin data and Signal data export dialogs received additional options on what kind of file header should be created. The Line separator option allows to to specify the line style ending.

Enhancements

Changed menu item 'Generate constraint file...' into 'Write constraint file...'
Html report: removed constraint columns from pin tables when no constraints are present. Improved empty table headers.
Added netlist pattern for shields
Show LVDS partner of a pin in the tooltip.
Added filter item (Pin view and Device view) to hide all pins which are equal on current and alternate device.
Improved automatic detection of RINF netlist files (when extension is not .frs or .frp).
Added a maximum zoom rate to the device view.

FPGA vendor and device support changes

AMD
Renamed Xilinx to AMD.
Device updates and new families for VersalHBM, VersalAiEdge, VersalPrime, VersalPremium, QVersalPremium, Zynqup.
Efinix
Devices updates for Trion and Titanium families.
Intel
Device updates for Agilex, Stratix10, MAX10
Renamed the Agilex family to Agilex-7
Set Stratix3, Stratix4 and Cyclone4 to be legacy families.
Lattice
Device updates for Avant, MachXO2, MachXO3, MachXO5, ECP5
Split the MachXO3 family into MachXO3L, MachXO3LF and MachXO3LFP.
Microsemi
Device updates for Igloo2, SmartFusion2, PolarFire, PolarfireSoc.
Support for the PolarFire pinlist format file ’...boardlayout.xml’.

Availability and Pricing

IO Checker 5.1 is available now. Prices begin at € 800 or US$ 870.
IO Checker can be downloaded and evaluated from the HDL Works website.

About HDL Works

HDL Works develops and markets high-performance, intuitive tools for complex HDL design across a wide spectrum of applications. HDL Works currently holds BoardTrace, EASE, HDL Companion and IO Checker in its product portfolio. Headquartered in Ede, The Netherlands, HDL Works is privately held.

HDL Works BV
Keperlaan 12
6716 BS Ede
The Netherlands

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BoardTrace, EASE, HDL Companion, IO Checker and Scriptum are trademarks of HDL Works.