What's new in HDL Companion 3.3

VHDL 2019

The VHDL parser in 2019 mode contains numerous improvements like:

• Allow a configuration to exist in another library than the entity.
• Allow the ‘;’ character after the last element of an interface list before the ‘)’ character.
• Allow ‘OPEN’ in partially associated formal of a component map.

Linting

Three new lint checks from the DO-254 Safe Synthesis list have been added:

• SS8: Avoid clock used as data
• SS9: Avoid shared clock and reset signal
• SS10: Avoid gated clocks

The above checks are only performed inside a Verilog module and VHDL architecture.

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