What's new in HDL Companion 3.3
The VHDL parser in 2019 mode contains numerous improvements like:
- Allow a configuration to exist in another library than the entity.
- Allow the ‘;’ character after the last element of an interface list before the ‘)’ character.
- Allow ‘OPEN’ in partially associated formal of a component map.
Three new lint checks from the DO-254 Safe Synthesis list have been added:
- SS8: Avoid clock used as data
- SS9: Avoid shared clock and reset signal
- SS10: Avoid gated clocks
The above checks are only performed inside a Verilog module and VHDL architecture.
The search widget options drop-down frame contains an explicit OK (Key Enter) and Cancel (Key ESC) buttons.
Clicking outside the option frame will cancel the selected options.
Try HDL Companion 3.3 now:
HDL Companion 3.3 can be downloaded from our website using the link below.
Copyright © 2004 - 2023 HDL Works