Generated by Ease for demo on Thu Jan 13 15:19:29 2022

Documentation for implementation receiver.rec_fsm.structure

Contents Side Data Generated HDL

FSM conditions:

Label Name Usage Verilog
1
~resetn
1
rx_falling
1
pos_rxclk && !rx
1
pos_rxclk && rx
1
pos_rxclk && end_data 
&& parity_en
1
pos_rxclk && end_data
1
pos_rxclk && 
stop_2bit
1
pos_rxclk
1
~stop_2bit
1
pos_rxclk

FSM actions:

Label Name Usage Verilog
def2
rxrdy <= 1'b0;
cnt   <= 0;
end_data <= 1'b0;
start1
rxrdy <= 1'b0;
cnt   <= nr_dbits+4;
end_data <= 1'b0;
decr1
if (cnt == 0)
  end_data <= 1'b1;
cnt <= cnt - 1;
rdy2
rxrdy <= 1'b1;