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rec_fsm

Documentation for implementation receiver.rec_fsm.structure

    1  ////////////////////////////////////////////////////////////////////////////////
    2  // Object        : Module receiver.rec_fsm
    3  // Last modified : Thu Jan 13 15:17:14 2022
    4  ////////////////////////////////////////////////////////////////////////////////
    5  
    6  module rec_fsm (data, frame_err, nr_dbits, parity_en, parity_err, pos_rxclk, 
    7    resetn, rx, rx_falling, rxrdy, sclk, stop_2bit) ;
    8  
    9    parameter  dwidth = 8; // Data width parallel data
   10    output     [dwidth-1:0]data;
   11    reg        [dwidth-1:0]data;
   12    output     frame_err;
   13    reg        frame_err;
   14    input      [1:0]nr_dbits;
   15    input      parity_en;
   16    output     parity_err;
   17    reg        parity_err;
   18    input      pos_rxclk;
   19    input      resetn;
   20    input      rx;
   21    input      rx_falling;
   22    output     rxrdy;
   23    reg        rxrdy;
   24    input      sclk;
   25    input      stop_2bit;
   26    // State Machine Options:
   27    //  Clock : sclk (Rising edge).
   28    //  State assignment : Enumerate.
   29    //  State decoding : Case construct.
   30    //  Actions on transitions : Clocked.
   31    //  Actions on states : Clocked.
   32  
   33    parameter  [2:0]IDLE   = 0;
   34    parameter  [2:0]START  = 1;
   35    parameter  [2:0]SDATA  = 2;
   36    parameter  [2:0]PARITY = 3;
   37    parameter  [2:0]STOP   = 4;
   38    parameter  [2:0]STOP2  = 5;
   39  
   40    reg        [2:0]state; // Current State
   41    reg [2:0] cnt;
   42    reg [dwidth-1:0] d_i;
   43    reg par; 
   44    reg end_data;
   45  
   46  
   47  
   48    always @ (posedge sclk or negedge resetn)
   49    begin
   50      if (~resetn)
   51      begin
   52        d_i        <= 0;
   53        data       <= 0;
   54        parity_err <= 1'b0;
   55        frame_err  <= 1'b0;
   56        par        <= 1'b0;
   57      end
   58      else 
   59      begin
   60        if (pos_rxclk)
   61        begin
   62          if (state == SDATA)
   63          begin
   64            // shift d
   65            d_i[dwidth-1-1:0] <= d_i[dwidth-1:1];
   66            d_i[dwidth-1]     <= rx;
   67            par               <= par ^ rx;
   68          end
   69          if (state == PARITY)
   70            // check calculated parity
   71            if (par != rx)    
   72              parity_err <= 1'b1;
   73          if ((state == STOP) || (state == STOP2))
   74        begin     
   75            if (~rx)
   76              frame_err <= 1'b1;
   77            data      <= d_i;
   78          end
   79          if (state == IDLE)
   80          begin
   81            frame_err  <= 1'b0;
   82            parity_err <= 1'b0;
   83            par        <= 1'b0;
   84            d_i        <= 0;
   85          end
   86        end
   87      end      
   88           
   89    end 
   90  
   91  
   92  
   93  
   94  
   95  
   96  
   97  
   98  
   99  
  100  
  101  
  102    // state_decoding
  103    always @(posedge sclk or negedge resetn)
  104    begin : state_decoding
  105      if (~resetn) begin
  106        state <= IDLE ;
  107        // def:
  108        rxrdy <= 1'b0;
  109        cnt   <= 0;
  110        end_data <= 1'b0;
  111      end
  112      else begin
  113        case (state)
  114          IDLE: begin
  115            if (rx_falling) begin
  116              state <= START ;
  117              // start:
  118              rxrdy <= 1'b0;
  119              cnt   <= nr_dbits+4;
  120              end_data <= 1'b0;
  121            end else begin
  122              state <= IDLE ;
  123              // def:
  124              rxrdy <= 1'b0;
  125              cnt   <= 0;
  126              end_data <= 1'b0;
  127            end
  128          end
  129          START: begin
  130            if (pos_rxclk && rx) begin
  131              state <= IDLE ;
  132            end else if (pos_rxclk && !rx) begin
  133              state <= SDATA ;
  134            end
  135          end
  136          SDATA: begin
  137            if (
  138              pos_rxclk && end_data 
  139              && parity_en
  140              ) begin
  141              state <= PARITY ;
  142            end else if (pos_rxclk && end_data) begin
  143              state <= STOP ;
  144            end else if (pos_rxclk) begin
  145              state <= SDATA ;
  146              // decr:
  147              if (cnt == 0)
  148                end_data <= 1'b1;
  149              cnt <= cnt - 1;
  150            end
  151          end
  152          PARITY: begin
  153            if (pos_rxclk) begin
  154              state <= STOP ;
  155            end
  156          end
  157          STOP: begin
  158            if (
  159              pos_rxclk && 
  160              stop_2bit
  161              ) begin
  162              state <= STOP2 ;
  163            end else if (~stop_2bit) begin
  164              state <= IDLE ;
  165              // rdy:
  166              rxrdy <= 1'b1;
  167            end
  168          end
  169          STOP2: begin
  170              state <= IDLE ;
  171              // rdy:
  172              rxrdy <= 1'b1;
  173          end
  174        endcase
  175      end //  Reset & Clock
  176    end // of state_decoding
  177  
  178  endmodule // rec_fsm
  179  
  180