Generated by Ease for demo on Thu Jan 13 15:19:29 2022
Back Index receiver receiver structure

Documentation for always construct receiver.receiver.structure.baudal

Contents Side Data Generated HDL

Verilog contents

    1  // EASE/HDL begin //////////////////////////////////////////////////////////////
    2  //
    3  // Always Construct 'baudal' in implementation 'structure' of module 'receiver'.
    4  //
    5  ////////////////////////////////////////////////////////////////////////////////
    6  //
    7  // Copy of the interface signals:
    8  //
    9  // input  wire sclk;
   10  // output reg  rxclk;
   11  // input  wire resetn;
   12  // 
   13  // EASE/HDL end ////////////////////////////////////////////////////////////////
   14  
   15  always @(posedge sclk or resetn)
   16  
   17  begin : baudal  // EASE/HDL sens.list
   18    if (~resetn)
   19    begin
   20      rxclk <= 0;
   21      cnt   <= 0;
   22    end
   23    else
   24    begin
   25      if (cnt == 0)
   26        rxclk <= !rxclk;
   27      if (cnt == 7)
   28        cnt <= 0;
   29      else
   30        cnt <= cnt + 1;
   31    end    
   32  end // baudal
   33