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receiver

receiver

structure

Documentation for always construct receiver.receiver.structure.sync

Verilog contents

    1  // EASE/HDL begin //////////////////////////////////////////////////////////////
    2  //
    3  // Always Construct 'sync' in implementation 'structure' of module 'receiver'.
    4  //
    5  ////////////////////////////////////////////////////////////////////////////////
    6  //
    7  // Copy of the interface signals:
    8  //
    9  // input  wire rx;
   10  // input  wire sclk;
   11  // input  wire resetn;
   12  // output reg  rx_s;
   13  // output reg  rx_i;
   14  // input  reg  rx_i;
   15  // 
   16  // EASE/HDL end ////////////////////////////////////////////////////////////////
   17  
   18  always @(posedge sclk or negedge resetn)
   19  
   20  begin : sync  // EASE/HDL sens.list
   21    if (~resetn)  
   22    begin
   23      rx_i <= 0;
   24      rx_s <= 0;
   25    end
   26    else
   27    begin
   28      rx_s <= rx_i;
   29      rx_i <= rx;
   30    end  
   31      
   32  end // sync
   33