Back

Index

uart

clock_gen

Documentation for architecture uart.clock_gen.text

VHDL contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  --
    3  -- Architecture 'text' of entity 'clock_gen'.
    4  --
    5  --------------------------------------------------------------------------------
    6  --
    7  -- Copy of the interface declaration:
    8  --
    9  --   generic(
   10  --     Period : time := 50 ns);
   11  --   port (
   12  --     clk : out    std_logic);
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture text of clock_gen is
   17  
   18  BEGIN
   19  
   20      clk_gen : PROCESS
   21      BEGIN
   22          clk <= '0';
   23          WAIT FOR Period/2;
   24          clk <= '1';
   25          WAIT FOR Period/2;
   26      END PROCESS;
   27    
   28  end architecture text ; -- of clock_gen
   29  
   30  
   31  
   32  
   33  
   34  
   35  
   36  
   37  
   38  
   39  
   40  
   41