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cntrl

Documentation for architecture uart.cntrl.rtl

    1  --------------------------------------------------------------------------------
    2  -- Object        : Architecture uart.cntrl.rtl
    3  -- Last modified : Thu Jan 13 15:17:39 2022
    4  --------------------------------------------------------------------------------
    5  
    6  
    7  architecture rtl of cntrl is
    8   
    9  begin
   10  
   11  process(sclk, resetn)
   12  begin
   13    if resetn = '0' then
   14      parity_en <= '0';
   15      nr_dbits  <= (others => '0');
   16      stop_2bit <= '0';
   17    elsif rising_edge(sclk) then
   18      if csn = '0' and wr = '1' then
   19        case addr is
   20          when "01"   => nr_dbits  <= data(1 downto 0);
   21          when "10"   => parity_en <= data(0);
   22          when "11"   => stop_2bit <= data(0);
   23          when others =>
   24        end case;
   25      end if;
   26    end if;
   27  end process;    
   28  end architecture rtl ; -- of cntrl
   29  
   30