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cntrl

Documentation for architecture uart.cntrl.rtl

VHDL contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  --
    3  -- Architecture 'rtl' of entity 'cntrl'.
    4  --
    5  --------------------------------------------------------------------------------
    6  --
    7  -- Copy of the interface declaration:
    8  --
    9  --   generic(
   10  --     dwidth : natural := 8); -- Data width parallel data
   11  --   port (
   12  --     addr      : in     std_logic_vector(1 downto 0);
   13  --     csn       : in     std_logic;
   14  --     data      : in     std_logic_vector(dwidth-1 downto 0);
   15  --     nr_dbits  : out    std_logic_vector(1 downto 0);
   16  --     parity_en : out    std_logic;
   17  --     resetn    : in     std_logic;
   18  --     sclk      : in     std_logic;
   19  --     stop_2bit : out    std_logic;
   20  --     wr        : in     std_logic);
   21  -- 
   22  -- EASE/HDL end ----------------------------------------------------------------
   23  
   24  architecture rtl of cntrl is
   25   
   26  begin
   27  
   28  process(sclk, resetn)
   29  begin
   30    if resetn = '0' then
   31      parity_en <= '0';
   32      nr_dbits  <= (others => '0');
   33      stop_2bit <= '0';
   34    elsif rising_edge(sclk) then
   35      if csn = '0' and wr = '1' then
   36        case addr is
   37          when "01"   => nr_dbits  <= data(1 downto 0);
   38          when "10"   => parity_en <= data(0);
   39          when "11"   => stop_2bit <= data(0);
   40          when others =>
   41        end case;
   42      end if;
   43    end if;
   44  end process;    
   45  end architecture rtl ; -- of cntrl
   46  
   47