Documentation for architecture uart.stim.rtl
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7 architecture rtl of stim is
8
9 signal baud_clk : std_logic := '0';
10 signal baudcnt : natural := 0;
11 signal parity_en : std_logic := '0';
12 signal nr_dbits : natural := 8;
13 signal stop_2bit : std_logic := '0';
14 signal rx_in : std_logic := '1';
15 signal loop_mode : std_logic := '0';
16
17 procedure init (signal addr : inout std_logic_vector(1 downto 0);
18 signal data : inout std_logic_vector(dwidth-1 downto 0);
19 signal csn : inout std_logic;
20 signal wr : inout std_logic;
21 signal rd : inout std_logic;
22 signal resetn : inout std_logic) is
23 begin
24 addr <= "00";
25 csn <= '1';
26 data <= (others => 'Z');
27 rd <= '0';
28 wr <= '0';
29 resetn <= '0';
30 wait for 2*Period;
31 resetn <= '1';
32 wait for Period;
33 end init;
34
35 procedure config( signal addr : inout std_logic_vector(1 downto 0);
36 signal data : inout std_logic_vector(dwidth-1 downto 0);
37 signal csn : inout std_logic;
38 signal wr : inout std_logic;
39 adr_in : in std_logic_vector(1 downto 0);
40 d_in : in std_logic_vector(dwidth-1 downto 0)) is
41 begin
42 wait for Period - 15 ns;
43 addr <= adr_in;
44 csn <= '0';
45 data <= d_in;
46 wr <= '1';
47 wait for Period;
48 csn <= '1';
49 wr <= '0';
50 data <= (others => 'Z');
51 wait for Period;
52 end config;
53
54 procedure config_nrdbits(
55 signal addr : inout std_logic_vector(1 downto 0);
56 signal data : inout std_logic_vector(dwidth-1 downto 0);
57 signal csn : inout std_logic;
58 signal wr : inout std_logic;
59 d_in : in natural) is
60 variable d : std_logic_vector(dwidth-1 downto 0) := (others => '0');
61 begin
62 d(1 downto 0) := conv_std_logic_vector((d_in-5), 2);
63 config(addr, data, csn, wr, "01", d);
64 end config_nrdbits;
65
66 procedure config_parity(
67 signal addr : inout std_logic_vector(1 downto 0);
68 signal data : inout std_logic_vector(dwidth-1 downto 0);
69 signal csn : inout std_logic;
70 signal wr : inout std_logic;
71 d_in : in std_logic) is
72 variable d : std_logic_vector(dwidth-1 downto 0) := (others => '0');
73 begin
74 d(0) := d_in;
75 config(addr, data, csn, wr, "10", d);
76 end config_parity;
77
78 procedure config_stop2bit(
79 signal addr : inout std_logic_vector(1 downto 0);
80 signal data : inout std_logic_vector(dwidth-1 downto 0);
81 signal csn : inout std_logic;
82 signal wr : inout std_logic;
83 d_in : in std_logic) is
84 variable d : std_logic_vector(dwidth-1 downto 0) := (others => '0');
85 begin
86 d(0) := d_in;
87 config(addr, data, csn, wr, "11", d);
88 end config_stop2bit;
89
90 procedure write_trans_data( signal addr : inout std_logic_vector(1 downto 0);
91 signal data : inout std_logic_vector(dwidth-1 downto 0);
92 signal csn : inout std_logic;
93 signal wr : inout std_logic;
94 d_in : in std_logic_vector(dwidth-1 downto 0)) is
95 begin
96 wait for Period - 15 ns;
97 addr <= "00";
98 csn <= '0';
99 data <= d_in;
100 wr <= '1';
101 wait for Period;
102 csn <= '1';
103 wr <= '0';
104 data <= (others => 'Z');
105 wait for 1 ns;
106 end write_trans_data;
107
108 procedure check_trans_data(signal tx : in std_logic;
109 signal txrdy: in std_logic;
110 d_in : in std_logic_vector(dwidth-1 downto 0)) is
111 variable length : integer;
112 variable par : std_logic := '0';
113 begin
114 length := nr_dbits;
115
116
117 wait until tx = '0';
118 wait until rising_edge(baud_clk);
119 if tx = '0' then
120 assert false report "Start bit detected" severity note;
121 else
122 assert false report "Start bit error" severity error;
123 end if;
124
125
126 for i in 0 to length-1 loop
127 wait until rising_edge(baud_clk);
128 if (tx /= d_in(i)) then
129 assert false report "Data bit error" severity error;
130 end if;
131 par := par XOR d_in(i);
132 end loop;
133
134 if txrdy /= '0' then
135 assert false report "Txrdy error" severity error;
136 end if;
137
138
139 wait until rising_edge(baud_clk);
140 if parity_en = '1' then
141 if tx = par then
142 assert false report "Parity bit verified" severity note;
143 else
144 assert false report "Parity bit error" severity error;
145 end if;
146
147
148 wait until rising_edge(baud_clk);
149 if tx = '1' then
150 assert false report "Stop bit detected" severity note;
151 else
152 assert false report "Stop bit error" severity error;
153 end if;
154 if txrdy /= '1' then
155 assert false report "Txrdy error" severity error;
156 end if;
157 else
158 assert false report "Parity disabled" severity note;
159
160 if tx = '1' then
161 assert false report "Stop bit detected" severity note;
162 else
163 assert false report "Stop bit error" severity error;
164 end if;
165
166 if txrdy /= '1' then
167 assert false report "Txrdy error" severity error;
168 end if;
169 end if;
170
171 if stop_2bit = '1' then
172 assert false report "Second stop bit enabled" severity note;
173 wait until rising_edge(baud_clk);
174 if tx /= '1' then
175 assert false report "Second stop bit error" severity error;
176 end if;
177 end if;
178
179 wait until txrdy = '0' for 1000 ns;
180 if txrdy /= '0' then
181 assert false report "Txrdy error" severity error;
182 end if;
183
184 end check_trans_data;
185
186 procedure trans_data(signal addr : inout std_logic_vector(1 downto 0);
187 signal data : inout std_logic_vector(dwidth-1 downto 0);
188 signal csn : inout std_logic;
189 signal wr : inout std_logic;
190 d_in : in std_logic_vector(dwidth-1 downto 0);
191 signal tx : in std_logic;
192 signal txrdy: in std_logic) is
193 begin
194 write_trans_data(addr, data, csn, wr, d_in);
195 check_trans_data(tx, txrdy, d_in);
196 end trans_data;
197
198 procedure check_rec_data(
199 signal data : inout std_logic_vector(dwidth-1 downto 0);
200 signal rd : inout std_logic;
201 signal rx : in std_logic;
202 signal rxrdy: in std_logic) is
203 variable length : integer;
204 variable par : std_logic := '0';
205 variable par_error, fr_error : std_logic := '0';
206 variable d : std_logic_vector(dwidth-1 downto 0) := (others => '0');
207 begin
208 assert false report "Receiver test" severity note;
209 length := nr_dbits;
210
211
212 wait until rx = '0';
213 wait until rising_edge(baud_clk);
214
215
216 for i in 0 to length-1 loop
217 wait until rising_edge(baud_clk);
218 d(dwidth-1-1 downto 0) := d(dwidth-1 downto 1);
219 d(dwidth-1) := rx;
220 par := par XOR rx;
221 end loop;
222
223
224 wait until rising_edge(baud_clk);
225 if parity_en = '1' then
226 if rx /= par then
227 assert false report "Parity bit error" severity error;
228 par_error := '1';
229 end if;
230
231
232 wait until rising_edge(baud_clk);
233 if rx /= '1' then
234 assert false report "Stop bit error" severity error;
235 fr_error := '1';
236 end if;
237 else
238
239 if rx /= '1' then
240 assert false report "Stop bit error" severity error;
241 fr_error := '1';
242 end if;
243 end if;
244
245
246 if stop_2bit = '1' then
247 wait until rising_edge(baud_clk);
248 if rx /= '1' then
249 assert false report "Second stop bit error" severity error;
250 fr_error := '1';
251 end if;
252 end if;
253
254 if rxrdy /= '1' then
255 wait until rxrdy = '1' for 1000 ns;
256 if rxrdy /= '1' then
257 assert false report "Rxrdy error" severity error;
258 end if;
259 end if;
260
261 rd <= '1';
262 wait for Period;
263
264 if data /= d then
265 assert false report "Wrong data received" severity error;
266 end if;
267 if parity_err /= par_error then
268 assert false report "Wrong parity error" severity error;
269 end if;
270 if frame_err /= fr_error then
271 assert false report "Wrong frame error" severity error;
272 end if;
273
274 rd <= '0';
275 wait for 1 ns;
276 end check_rec_data;
277
278 procedure rec_data(signal addr : inout std_logic_vector(1 downto 0);
279 signal data : inout std_logic_vector(dwidth-1 downto 0);
280 signal csn : inout std_logic;
281 signal wr : inout std_logic;
282 signal rd : inout std_logic;
283 d_in : in std_logic_vector(dwidth-1 downto 0);
284 signal rx : in std_logic;
285 signal rxrdy: in std_logic;
286 signal loop_mode : inout std_logic) is
287 begin
288
289 loop_mode <= '1';
290
291 write_trans_data(addr, data, csn, wr, d_in);
292 check_rec_data(data, rd, rx, rxrdy);
293 end rec_data;
294
295
296 procedure transmitter_test(signal addr : inout std_logic_vector(1 downto 0);
297 signal data : inout std_logic_vector(dwidth-1 downto 0);
298 signal csn : inout std_logic;
299 signal wr : inout std_logic;
300 signal tx : in std_logic;
301 signal txrdy: in std_logic;
302 signal nr_dbits : inout natural;
303 signal parity_en : inout std_logic;
304 signal stop_2bit : inout std_logic) is
305 variable d_in : std_logic_vector(dwidth-1 downto 0);
306 begin
307
308 nr_dbits <= 8; parity_en <= '0'; stop_2bit <= '0';
309 config_nrdbits(addr, data, csn, wr, 8);
310 config_parity(addr, data, csn, wr, '0');
311 config_stop2bit(addr, data, csn, wr, '0');
312
313
314 d_in := "10100110";
315 trans_data(addr, data, csn, wr, d_in, tx, txrdy);
316
317
318 parity_en <= '1';
319 config_parity(addr, data, csn, wr, '1');
320
321
322 d_in := "01101001";
323 trans_data(addr, data, csn, wr, d_in, tx, txrdy);
324
325
326 stop_2bit <= '1';
327 config_stop2bit(addr, data, csn, wr, '1');
328
329
330 d_in := "11100101";
331 trans_data(addr, data, csn, wr, d_in, tx, txrdy);
332
333
334 nr_dbits <= 5; parity_en <= '1'; stop_2bit <= '0';
335 config_nrdbits(addr, data, csn, wr, 5);
336 config_parity(addr, data, csn, wr, '1');
337 config_stop2bit(addr, data, csn, wr, '0');
338
339
340 d_in := (others => '0');
341 d_in(4 downto 0) := "00101";
342 trans_data(addr, data, csn, wr, d_in, tx, txrdy);
343 end transmitter_test;
344
345
346 procedure receiver_test(signal addr : inout std_logic_vector(1 downto 0);
347 signal data : inout std_logic_vector(dwidth-1 downto 0);
348 signal csn : inout std_logic;
349 signal wr : inout std_logic;
350 signal rd : inout std_logic;
351 signal txrdy: in std_logic;
352 signal rx : in std_logic;
353 signal rxrdy: in std_logic;
354 signal loop_mode : inout std_logic;
355 signal nr_dbits : inout natural;
356 signal parity_en : inout std_logic;
357 signal stop_2bit : inout std_logic) is
358 variable d_in : std_logic_vector(dwidth-1 downto 0);
359 begin
360
361 nr_dbits <= 8; parity_en <= '0'; stop_2bit <= '0';
362 config_nrdbits(addr, data, csn, wr, 8);
363 config_parity(addr, data, csn, wr, '0');
364 config_stop2bit(addr, data, csn, wr, '0');
365
366
367 if txrdy /= '0' then
368 wait until txrdy = '0' for 20 us;
369 if txrdy /= '0' then
370 assert false report "Txrdy error" severity failure;
371 end if;
372 end if;
373 d_in := "10100110";
374 rec_data(addr, data, csn, wr, rd, d_in, rx, rxrdy, loop_mode);
375
376
377 parity_en <= '1';
378 config_parity(addr, data, csn, wr, '1');
379
380
381 if txrdy /= '0' then
382 wait until txrdy = '0' for 20 us;
383 if txrdy /= '0' then
384 assert false report "Txrdy error" severity failure;
385 end if;
386 end if;
387 d_in := "01101001";
388 rec_data(addr, data, csn, wr, rd, d_in, rx, rxrdy, loop_mode);
389
390
391 stop_2bit <= '1';
392 config_stop2bit(addr, data, csn, wr, '1');
393
394
395 if txrdy /= '0' then
396 wait until txrdy = '0' for 20 us;
397 if txrdy /= '0' then
398 assert false report "Txrdy error" severity failure;
399 end if;
400 end if;
401 d_in := "11100101";
402 rec_data(addr, data, csn, wr, rd, d_in, rx, rxrdy, loop_mode);
403
404
405 nr_dbits <= 5; parity_en <= '1'; stop_2bit <= '0';
406 config_nrdbits(addr, data, csn, wr, 5);
407 config_parity(addr, data, csn, wr, '1');
408 config_stop2bit(addr, data, csn, wr, '0');
409
410
411 if txrdy /= '0' then
412 wait until txrdy = '0' for 20 us;
413 if txrdy /= '0' then
414 assert false report "Txrdy error" severity failure;
415 end if;
416 end if;
417 d_in := (others => '0');
418 d_in(4 downto 0) := "00101";
419 rec_data(addr, data, csn, wr, rd, d_in, rx, rxrdy, loop_mode);
420 end receiver_test;
421
422
423 procedure rx_mux(signal tx, rx_in: in std_logic;
424 signal rx: inout std_logic) is
425 begin
426 if loop_mode = '1' then
427 rx <= tx;
428 else
429 rx <= rx_in;
430 end if;
431 end rx_mux;
432
433 begin
434
435 rx_mux(tx, rx_in, rx);
436
437 baudproc : process(sclk)
438 begin
439 if rising_edge(sclk) then
440 if baudcnt = 0 then
441 baud_clk <= not baud_clk;
442 end if;
443 if baudcnt = 7 then
444 baudcnt <= 0;
445 else
446 baudcnt <= baudcnt + 1;
447 end if;
448 end if;
449 end process;
450
451 stimproc : process
452 begin
453 init(addr, data, csn, wr, rd, resetn);
454
455 transmitter_test(addr, data, csn, wr, tx, txrdy, nr_dbits, parity_en, stop_2bit);
456
457 receiver_test(addr, data, csn, wr, rd, txrdy, rx, rxrdy, loop_mode, nr_dbits, parity_en, stop_2bit);
458
459 assert false report "End of stimulus" severity failure;
460 wait;
461 end process;
462
463 end architecture rtl ;
464
465
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uart
stim