Documentation for architecture uart.stim.rtl
VHDL contents
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29 architecture rtl of stim is
30
31 signal baud_clk : std_logic := '0';
32 signal baudcnt : natural := 0;
33 signal parity_en : std_logic := '0';
34 signal nr_dbits : natural := 8;
35 signal stop_2bit : std_logic := '0';
36 signal rx_in : std_logic := '1';
37 signal loop_mode : std_logic := '0';
38
39 procedure init (signal addr : inout std_logic_vector(1 downto 0);
40 signal data : inout std_logic_vector(dwidth-1 downto 0);
41 signal csn : inout std_logic;
42 signal wr : inout std_logic;
43 signal rd : inout std_logic;
44 signal resetn : inout std_logic) is
45 begin
46 addr <= "00";
47 csn <= '1';
48 data <= (others => 'Z');
49 rd <= '0';
50 wr <= '0';
51 resetn <= '0';
52 wait for 2*Period;
53 resetn <= '1';
54 wait for Period;
55 end init;
56
57 procedure config( signal addr : inout std_logic_vector(1 downto 0);
58 signal data : inout std_logic_vector(dwidth-1 downto 0);
59 signal csn : inout std_logic;
60 signal wr : inout std_logic;
61 adr_in : in std_logic_vector(1 downto 0);
62 d_in : in std_logic_vector(dwidth-1 downto 0)) is
63 begin
64 wait for Period - 15 ns;
65 addr <= adr_in;
66 csn <= '0';
67 data <= d_in;
68 wr <= '1';
69 wait for Period;
70 csn <= '1';
71 wr <= '0';
72 data <= (others => 'Z');
73 wait for Period;
74 end config;
75
76 procedure config_nrdbits(
77 signal addr : inout std_logic_vector(1 downto 0);
78 signal data : inout std_logic_vector(dwidth-1 downto 0);
79 signal csn : inout std_logic;
80 signal wr : inout std_logic;
81 d_in : in natural) is
82 variable d : std_logic_vector(dwidth-1 downto 0) := (others => '0');
83 begin
84 d(1 downto 0) := conv_std_logic_vector((d_in-5), 2);
85 config(addr, data, csn, wr, "01", d);
86 end config_nrdbits;
87
88 procedure config_parity(
89 signal addr : inout std_logic_vector(1 downto 0);
90 signal data : inout std_logic_vector(dwidth-1 downto 0);
91 signal csn : inout std_logic;
92 signal wr : inout std_logic;
93 d_in : in std_logic) is
94 variable d : std_logic_vector(dwidth-1 downto 0) := (others => '0');
95 begin
96 d(0) := d_in;
97 config(addr, data, csn, wr, "10", d);
98 end config_parity;
99
100 procedure config_stop2bit(
101 signal addr : inout std_logic_vector(1 downto 0);
102 signal data : inout std_logic_vector(dwidth-1 downto 0);
103 signal csn : inout std_logic;
104 signal wr : inout std_logic;
105 d_in : in std_logic) is
106 variable d : std_logic_vector(dwidth-1 downto 0) := (others => '0');
107 begin
108 d(0) := d_in;
109 config(addr, data, csn, wr, "11", d);
110 end config_stop2bit;
111
112 procedure write_trans_data( signal addr : inout std_logic_vector(1 downto 0);
113 signal data : inout std_logic_vector(dwidth-1 downto 0);
114 signal csn : inout std_logic;
115 signal wr : inout std_logic;
116 d_in : in std_logic_vector(dwidth-1 downto 0)) is
117 begin
118 wait for Period - 15 ns;
119 addr <= "00";
120 csn <= '0';
121 data <= d_in;
122 wr <= '1';
123 wait for Period;
124 csn <= '1';
125 wr <= '0';
126 data <= (others => 'Z');
127 wait for 1 ns;
128 end write_trans_data;
129
130 procedure check_trans_data(signal tx : in std_logic;
131 signal txrdy: in std_logic;
132 d_in : in std_logic_vector(dwidth-1 downto 0)) is
133 variable length : integer;
134 variable par : std_logic := '0';
135 begin
136 length := nr_dbits;
137
138
139 wait until tx = '0';
140 wait until rising_edge(baud_clk);
141 if tx = '0' then
142 assert false report "Start bit detected" severity note;
143 else
144 assert false report "Start bit error" severity error;
145 end if;
146
147
148 for i in 0 to length-1 loop
149 wait until rising_edge(baud_clk);
150 if (tx /= d_in(i)) then
151 assert false report "Data bit error" severity error;
152 end if;
153 par := par XOR d_in(i);
154 end loop;
155
156 if txrdy /= '0' then
157 assert false report "Txrdy error" severity error;
158 end if;
159
160
161 wait until rising_edge(baud_clk);
162 if parity_en = '1' then
163 if tx = par then
164 assert false report "Parity bit verified" severity note;
165 else
166 assert false report "Parity bit error" severity error;
167 end if;
168
169
170 wait until rising_edge(baud_clk);
171 if tx = '1' then
172 assert false report "Stop bit detected" severity note;
173 else
174 assert false report "Stop bit error" severity error;
175 end if;
176 if txrdy /= '1' then
177 assert false report "Txrdy error" severity error;
178 end if;
179 else
180 assert false report "Parity disabled" severity note;
181
182 if tx = '1' then
183 assert false report "Stop bit detected" severity note;
184 else
185 assert false report "Stop bit error" severity error;
186 end if;
187
188 if txrdy /= '1' then
189 assert false report "Txrdy error" severity error;
190 end if;
191 end if;
192
193 if stop_2bit = '1' then
194 assert false report "Second stop bit enabled" severity note;
195 wait until rising_edge(baud_clk);
196 if tx /= '1' then
197 assert false report "Second stop bit error" severity error;
198 end if;
199 end if;
200
201 wait until txrdy = '0' for 1000 ns;
202 if txrdy /= '0' then
203 assert false report "Txrdy error" severity error;
204 end if;
205
206 end check_trans_data;
207
208 procedure trans_data(signal addr : inout std_logic_vector(1 downto 0);
209 signal data : inout std_logic_vector(dwidth-1 downto 0);
210 signal csn : inout std_logic;
211 signal wr : inout std_logic;
212 d_in : in std_logic_vector(dwidth-1 downto 0);
213 signal tx : in std_logic;
214 signal txrdy: in std_logic) is
215 begin
216 write_trans_data(addr, data, csn, wr, d_in);
217 check_trans_data(tx, txrdy, d_in);
218 end trans_data;
219
220 procedure check_rec_data(
221 signal data : inout std_logic_vector(dwidth-1 downto 0);
222 signal rd : inout std_logic;
223 signal rx : in std_logic;
224 signal rxrdy: in std_logic) is
225 variable length : integer;
226 variable par : std_logic := '0';
227 variable par_error, fr_error : std_logic := '0';
228 variable d : std_logic_vector(dwidth-1 downto 0) := (others => '0');
229 begin
230 assert false report "Receiver test" severity note;
231 length := nr_dbits;
232
233
234 wait until rx = '0';
235 wait until rising_edge(baud_clk);
236
237
238 for i in 0 to length-1 loop
239 wait until rising_edge(baud_clk);
240 d(dwidth-1-1 downto 0) := d(dwidth-1 downto 1);
241 d(dwidth-1) := rx;
242 par := par XOR rx;
243 end loop;
244
245
246 wait until rising_edge(baud_clk);
247 if parity_en = '1' then
248 if rx /= par then
249 assert false report "Parity bit error" severity error;
250 par_error := '1';
251 end if;
252
253
254 wait until rising_edge(baud_clk);
255 if rx /= '1' then
256 assert false report "Stop bit error" severity error;
257 fr_error := '1';
258 end if;
259 else
260
261 if rx /= '1' then
262 assert false report "Stop bit error" severity error;
263 fr_error := '1';
264 end if;
265 end if;
266
267
268 if stop_2bit = '1' then
269 wait until rising_edge(baud_clk);
270 if rx /= '1' then
271 assert false report "Second stop bit error" severity error;
272 fr_error := '1';
273 end if;
274 end if;
275
276 if rxrdy /= '1' then
277 wait until rxrdy = '1' for 1000 ns;
278 if rxrdy /= '1' then
279 assert false report "Rxrdy error" severity error;
280 end if;
281 end if;
282
283 rd <= '1';
284 wait for Period;
285
286 if data /= d then
287 assert false report "Wrong data received" severity error;
288 end if;
289 if parity_err /= par_error then
290 assert false report "Wrong parity error" severity error;
291 end if;
292 if frame_err /= fr_error then
293 assert false report "Wrong frame error" severity error;
294 end if;
295
296 rd <= '0';
297 wait for 1 ns;
298 end check_rec_data;
299
300 procedure rec_data(signal addr : inout std_logic_vector(1 downto 0);
301 signal data : inout std_logic_vector(dwidth-1 downto 0);
302 signal csn : inout std_logic;
303 signal wr : inout std_logic;
304 signal rd : inout std_logic;
305 d_in : in std_logic_vector(dwidth-1 downto 0);
306 signal rx : in std_logic;
307 signal rxrdy: in std_logic;
308 signal loop_mode : inout std_logic) is
309 begin
310
311 loop_mode <= '1';
312
313 write_trans_data(addr, data, csn, wr, d_in);
314 check_rec_data(data, rd, rx, rxrdy);
315 end rec_data;
316
317
318 procedure transmitter_test(signal addr : inout std_logic_vector(1 downto 0);
319 signal data : inout std_logic_vector(dwidth-1 downto 0);
320 signal csn : inout std_logic;
321 signal wr : inout std_logic;
322 signal tx : in std_logic;
323 signal txrdy: in std_logic;
324 signal nr_dbits : inout natural;
325 signal parity_en : inout std_logic;
326 signal stop_2bit : inout std_logic) is
327 variable d_in : std_logic_vector(dwidth-1 downto 0);
328 begin
329
330 nr_dbits <= 8; parity_en <= '0'; stop_2bit <= '0';
331 config_nrdbits(addr, data, csn, wr, 8);
332 config_parity(addr, data, csn, wr, '0');
333 config_stop2bit(addr, data, csn, wr, '0');
334
335
336 d_in := "10100110";
337 trans_data(addr, data, csn, wr, d_in, tx, txrdy);
338
339
340 parity_en <= '1';
341 config_parity(addr, data, csn, wr, '1');
342
343
344 d_in := "01101001";
345 trans_data(addr, data, csn, wr, d_in, tx, txrdy);
346
347
348 stop_2bit <= '1';
349 config_stop2bit(addr, data, csn, wr, '1');
350
351
352 d_in := "11100101";
353 trans_data(addr, data, csn, wr, d_in, tx, txrdy);
354
355
356 nr_dbits <= 5; parity_en <= '1'; stop_2bit <= '0';
357 config_nrdbits(addr, data, csn, wr, 5);
358 config_parity(addr, data, csn, wr, '1');
359 config_stop2bit(addr, data, csn, wr, '0');
360
361
362 d_in := (others => '0');
363 d_in(4 downto 0) := "00101";
364 trans_data(addr, data, csn, wr, d_in, tx, txrdy);
365 end transmitter_test;
366
367
368 procedure receiver_test(signal addr : inout std_logic_vector(1 downto 0);
369 signal data : inout std_logic_vector(dwidth-1 downto 0);
370 signal csn : inout std_logic;
371 signal wr : inout std_logic;
372 signal rd : inout std_logic;
373 signal txrdy: in std_logic;
374 signal rx : in std_logic;
375 signal rxrdy: in std_logic;
376 signal loop_mode : inout std_logic;
377 signal nr_dbits : inout natural;
378 signal parity_en : inout std_logic;
379 signal stop_2bit : inout std_logic) is
380 variable d_in : std_logic_vector(dwidth-1 downto 0);
381 begin
382
383 nr_dbits <= 8; parity_en <= '0'; stop_2bit <= '0';
384 config_nrdbits(addr, data, csn, wr, 8);
385 config_parity(addr, data, csn, wr, '0');
386 config_stop2bit(addr, data, csn, wr, '0');
387
388
389 if txrdy /= '0' then
390 wait until txrdy = '0' for 20 us;
391 if txrdy /= '0' then
392 assert false report "Txrdy error" severity failure;
393 end if;
394 end if;
395 d_in := "10100110";
396 rec_data(addr, data, csn, wr, rd, d_in, rx, rxrdy, loop_mode);
397
398
399 parity_en <= '1';
400 config_parity(addr, data, csn, wr, '1');
401
402
403 if txrdy /= '0' then
404 wait until txrdy = '0' for 20 us;
405 if txrdy /= '0' then
406 assert false report "Txrdy error" severity failure;
407 end if;
408 end if;
409 d_in := "01101001";
410 rec_data(addr, data, csn, wr, rd, d_in, rx, rxrdy, loop_mode);
411
412
413 stop_2bit <= '1';
414 config_stop2bit(addr, data, csn, wr, '1');
415
416
417 if txrdy /= '0' then
418 wait until txrdy = '0' for 20 us;
419 if txrdy /= '0' then
420 assert false report "Txrdy error" severity failure;
421 end if;
422 end if;
423 d_in := "11100101";
424 rec_data(addr, data, csn, wr, rd, d_in, rx, rxrdy, loop_mode);
425
426
427 nr_dbits <= 5; parity_en <= '1'; stop_2bit <= '0';
428 config_nrdbits(addr, data, csn, wr, 5);
429 config_parity(addr, data, csn, wr, '1');
430 config_stop2bit(addr, data, csn, wr, '0');
431
432
433 if txrdy /= '0' then
434 wait until txrdy = '0' for 20 us;
435 if txrdy /= '0' then
436 assert false report "Txrdy error" severity failure;
437 end if;
438 end if;
439 d_in := (others => '0');
440 d_in(4 downto 0) := "00101";
441 rec_data(addr, data, csn, wr, rd, d_in, rx, rxrdy, loop_mode);
442 end receiver_test;
443
444
445 procedure rx_mux(signal tx, rx_in: in std_logic;
446 signal rx: inout std_logic) is
447 begin
448 if loop_mode = '1' then
449 rx <= tx;
450 else
451 rx <= rx_in;
452 end if;
453 end rx_mux;
454
455 begin
456
457 rx_mux(tx, rx_in, rx);
458
459 baudproc : process(sclk)
460 begin
461 if rising_edge(sclk) then
462 if baudcnt = 0 then
463 baud_clk <= not baud_clk;
464 end if;
465 if baudcnt = 7 then
466 baudcnt <= 0;
467 else
468 baudcnt <= baudcnt + 1;
469 end if;
470 end if;
471 end process;
472
473 stimproc : process
474 begin
475 init(addr, data, csn, wr, rd, resetn);
476
477 transmitter_test(addr, data, csn, wr, tx, txrdy, nr_dbits, parity_en, stop_2bit);
478
479 receiver_test(addr, data, csn, wr, rd, txrdy, rx, rxrdy, loop_mode, nr_dbits, parity_en, stop_2bit);
480
481 assert false report "End of stimulus" severity failure;
482 wait;
483 end process;
484
485 end architecture rtl ;
486
487
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uart
stim