Documentation for architecture uart.transmit.fsm

resetn = '0'

ld = '1'

neg_txclk = '1'

neg_txclk = '1' and
parity_en = '1'

neg_txclk = '1'

neg_txclk = '1'

neg_txclk = '1' and
stop_2bit = '1'

neg_txclk = '1'

neg_txclk = '1' and
cnt /= 0

neg_txclk = '1'

neg_txclk = '1'

tx     <= data(0);
parity <= parity XOR data(0);
data   <= '0' & data(7 downto 1);
cnt    <= cnt - 1;

tx <= parity;

tx <= '1';
txrdy <= '1';

tx <= '0';

tx    <= '1';
txrdy <= '0';
data  <= (others => '0');
cnt   <= (others => '0');
parity<= '0';

data   <= d;
cnt    <= ('0'&nr_dbits) + 4;
parity <= '0';