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transmit

Documentation for architecture uart.transmit.fsm

    1  --------------------------------------------------------------------------------
    2  -- Object        : Architecture uart.transmit.fsm
    3  -- Last modified : Thu Jan 13 15:18:06 2022
    4  --------------------------------------------------------------------------------
    5  
    6  architecture fsm of transmit is
    7  
    8    -- State Machine Options:
    9    --  Clock : sclk (Rising edge).
   10    --  State assignment : Enumerate.
   11    --  State decoding : Case construct.
   12    --  Actions on transitions : Clocked.
   13    --  Actions on states : Clocked.
   14  
   15    type state_type is (idle, load, send_data, send_parity, send_stop, stop_mult, 
   16              wait_stop) ;
   17    signal state : state_type;  -- Current State
   18    signal data   : std_logic_vector(dwidth-1 downto 0);
   19    signal cnt    : std_logic_vector(2 downto 0);
   20    signal parity : std_logic;
   21  
   22  
   23  begin
   24    state_decoding: process (sclk, resetn) is
   25    begin
   26      if (resetn = '0') then
   27        state <= idle ;
   28        -- def:
   29        tx    <= '1';
   30        txrdy <= '0';
   31        data  <= (others => '0');
   32        cnt   <= (others => '0');
   33        parity<= '0';
   34      elsif (sclk'event and (sclk = '1')) then
   35        lbl_state : case state is
   36          when idle =>
   37            if (ld = '1') then
   38              state <= load ;
   39              -- tx_ld:
   40              data   <= d;
   41              cnt    <= ('0'&nr_dbits) + 4;
   42              parity <= '0';
   43            end if ;
   44          when load =>
   45            if (neg_txclk = '1') then
   46              state <= send_data ;
   47              -- tx_start:
   48              tx <= '0';
   49            end if ;
   50          when send_data =>
   51            if (
   52              neg_txclk = '1' and
   53              cnt /= 0
   54              ) then
   55              state <= send_data ;
   56              -- tx_data:
   57              tx     <= data(0);
   58              parity <= parity XOR data(0);
   59              data   <= '0' & data(7 downto 1);
   60              cnt    <= cnt - 1;
   61  
   62            elsif (
   63              neg_txclk = '1' and
   64              parity_en = '1'
   65              ) then
   66              state <= send_parity ;
   67              -- tx_data:
   68              tx     <= data(0);
   69              parity <= parity XOR data(0);
   70              data   <= '0' & data(7 downto 1);
   71              cnt    <= cnt - 1;
   72  
   73            elsif (neg_txclk = '1') then
   74              state <= send_stop ;
   75              -- tx_data:
   76              tx     <= data(0);
   77              parity <= parity XOR data(0);
   78              data   <= '0' & data(7 downto 1);
   79              cnt    <= cnt - 1;
   80  
   81            end if ;
   82          when send_parity =>
   83            if (neg_txclk = '1') then
   84              state <= send_stop ;
   85              tx <= parity;
   86            end if ;
   87          when send_stop =>
   88            if (
   89              neg_txclk = '1' and
   90              stop_2bit = '1'
   91              ) then
   92              state <= stop_mult ;
   93              -- tx_stop:
   94              tx <= '1';
   95              txrdy <= '1';
   96            elsif (neg_txclk = '1') then
   97              state <= wait_stop ;
   98              -- tx_stop:
   99              tx <= '1';
  100              txrdy <= '1';
  101            end if ;
  102          when stop_mult =>
  103            if (neg_txclk = '1') then
  104              state <= wait_stop ;
  105              -- tx_stop:
  106              tx <= '1';
  107              txrdy <= '1';
  108            end if ;
  109          when wait_stop =>
  110            if (neg_txclk = '1') then
  111              state <= idle ;
  112              -- def:
  113              tx    <= '1';
  114              txrdy <= '0';
  115              data  <= (others => '0');
  116              cnt   <= (others => '0');
  117              parity<= '0';
  118            end if ;
  119        end case lbl_state ;
  120      end if ; --  Reset & Clock
  121    end process state_decoding ;
  122  
  123  end architecture fsm ; -- of transmit
  124  
  125